diff mbox

[04/10] target-s390: Raise OPERATION exception for disabled insns

Message ID 1379945085-29086-5-git-send-email-rth@twiddle.net
State New
Headers show

Commit Message

Richard Henderson Sept. 23, 2013, 2:04 p.m. UTC 
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-s390x/translate.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)
diff mbox

Patch

diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 5aac7b0..c8bbedb 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -53,6 +53,7 @@  struct DisasContext {
     const DisasInsn *insn;
     DisasFields *fields;
     uint64_t pc, next_pc;
+    uint64_t fac0;
     enum cc_op cc_op;
     bool singlestep_enabled;
 };
@@ -4651,6 +4652,16 @@  static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
         return EXIT_NORETURN;
     }
 
+    /* Check for operation exceptions for insns that have been disabled.
+       Do this by shifting the facilities word0 up by the IBM big-endian
+       bit numbering, leaving the bit to be tested in the sign bit.
+       Note that TCG does not currently support any facilities in word1.  */
+    assert(insn->fac < 64);
+    if ((int64_t)(s->fac0 << insn->fac) >= 0) {
+        gen_program_exception(s, PGM_OPERATION);
+        return EXIT_NORETURN;
+    }
+
     /* Check for insn specification exceptions.  */
     if (insn->spec) {
         int spec = insn->spec, excp = 0, r;
@@ -4769,6 +4780,7 @@  static inline void gen_intermediate_code_internal(S390CPU *cpu,
     dc.tb = tb;
     dc.pc = pc_start;
     dc.cc_op = CC_OP_DYNAMIC;
+    dc.fac0 = env->facilities[0];
     do_debug = dc.singlestep_enabled = cs->singlestep_enabled;
 
     gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;