From patchwork Sun Sep 15 00:03:50 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 274994 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9AD302C010F for ; Sun, 15 Sep 2013 10:06:31 +1000 (EST) Received: from localhost ([::1]:54987 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VKzrB-0002Qu-BF for incoming@patchwork.ozlabs.org; Sat, 14 Sep 2013 20:06:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48204) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VKzoz-0007YE-3N for qemu-devel@nongnu.org; Sat, 14 Sep 2013 20:04:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VKzos-00010y-Bg for qemu-devel@nongnu.org; Sat, 14 Sep 2013 20:04:13 -0400 Received: from mail-pb0-x235.google.com ([2607:f8b0:400e:c01::235]:62797) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VKzor-00010u-W3; Sat, 14 Sep 2013 20:04:06 -0400 Received: by mail-pb0-f53.google.com with SMTP id up15so2649171pbc.26 for ; Sat, 14 Sep 2013 17:04:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=1jqUekvdIiKpMI/0ySGZt3eMwS3Vvqtotyu21bEMLXY=; b=ipa6irIb0VVwvKT5Wc53qJmKdYEN7PD/GfyULa2rhvxftZfzvaASCyNusCtbTrC2Nj AM+Kcp5OZCKxwbIkMssauDhpTeERTo+NtMHeQmuS4z1wsWSN2RBHMzjc2XVtRBjRCaDL zf6eix5/OeULaOIshU37zU8p/ellT//dbq4PZaEmrXSGbolXD9/wdnjZt0MOEyGkK8wt 7UgSEO8syswhLnJtvqbjqXSO2a2hIUrIs4TV2XVTijbrNlC59jo7JuEjQh1hR0XqzD1d j9tWcovzmGT+mDooj/SvGX14vSwVQKDsaJwWWWx9hZlcD/cFGTJR07Fg2YqBsTmkRFrO 81Bg== X-Received: by 10.68.64.201 with SMTP id q9mr21225789pbs.15.1379203444949; Sat, 14 Sep 2013 17:04:04 -0700 (PDT) Received: from anchor.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPSA id vz4sm27763065pab.11.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sat, 14 Sep 2013 17:04:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 14 Sep 2013 17:03:50 -0700 Message-Id: <1379203434-5680-5-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1379203434-5680-1-git-send-email-rth@twiddle.net> References: <1379203434-5680-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c01::235 Cc: peter.maydell@linaro.org, Jia Liu , sw@weilnetz.de, Alexander Graf , Blue Swirl , Max Filippov , "open list:PowerPC" , Paul Brook , "Edgar E. Iglesias" , Guan Xuetao , aurelien@aurel32.net, Richard Henderson Subject: [Qemu-devel] [PATCH 4/8] tcg: Move helper registration into tcg_context_init X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org No longer needs to be done on a per-target basis. Signed-off-by: Richard Henderson --- target-alpha/translate.c | 4 ---- target-arm/translate.c | 3 --- target-cris/translate.c | 3 --- target-i386/translate.c | 4 ---- target-m68k/translate.c | 3 --- target-microblaze/translate.c | 2 -- target-mips/translate.c | 4 ---- target-openrisc/translate.c | 2 -- target-ppc/translate.c | 4 ---- target-s390x/translate.c | 4 ---- target-sh4/translate.c | 4 ---- target-sparc/translate.c | 5 ----- target-unicore32/translate.c | 3 --- target-xtensa/translate.c | 2 -- tcg/tcg.c | 8 +++++++- 15 files changed, 7 insertions(+), 48 deletions(-) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 28ce436..9cb8084 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -140,10 +140,6 @@ void alpha_translate_init(void) offsetof(CPUAlphaState, usp), "usp"); #endif - /* register helpers */ -#define GEN_HELPER 2 -#include "helper.h" - done_init = 1; } diff --git a/target-arm/translate.c b/target-arm/translate.c index 998bde2..5f003e7 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -115,9 +115,6 @@ void arm_translate_init(void) #endif a64_translate_init(); - -#define GEN_HELPER 2 -#include "helper.h" } static inline TCGv_i32 load_cpu_offset(int offset) diff --git a/target-cris/translate.c b/target-cris/translate.c index 617e1b4..5faa44c 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3480,9 +3480,6 @@ void cris_initialize_tcg(void) { int i; -#define GEN_HELPER 2 -#include "helper.h" - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); cc_x = tcg_global_mem_new(TCG_AREG0, offsetof(CPUCRISState, cc_x), "cc_x"); diff --git a/target-i386/translate.c b/target-i386/translate.c index 6d87900..439fc5a 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -8242,10 +8242,6 @@ void optimize_flags_init(void) cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUX86State, regs[R_EDI]), "edi"); #endif - - /* register helpers */ -#define GEN_HELPER 2 -#include "helper.h" } /* generate intermediate code in gen_opc_buf and gen_opparam_buf for diff --git a/target-m68k/translate.c b/target-m68k/translate.c index f31e48d..f54b94a 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -108,9 +108,6 @@ void m68k_tcg_init(void) NULL_QREG = tcg_global_mem_new(TCG_AREG0, -4, "NULL"); store_dummy = tcg_global_mem_new(TCG_AREG0, -8, "NULL"); - -#define GEN_HELPER 2 -#include "helper.h" } static inline void qemu_assert(int cond, const char *msg) diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 0673176..1b937b3 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -2024,8 +2024,6 @@ void mb_tcg_init(void) offsetof(CPUMBState, sregs[i]), special_regnames[i]); } -#define GEN_HELPER 2 -#include "helper.h" } void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, int pc_pos) diff --git a/target-mips/translate.c b/target-mips/translate.c index ad43d59..0d8db66 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -15886,10 +15886,6 @@ void mips_tcg_init(void) offsetof(CPUMIPSState, active_fpu.fcr31), "fcr31"); - /* register helpers */ -#define GEN_HELPER 2 -#include "helper.h" - inited = 1; } diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 723b77d..8908a2e 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -110,8 +110,6 @@ void openrisc_translate_init(void) offsetof(CPUOpenRISCState, gpr[i]), regnames[i]); } -#define GEN_HELPER 2 -#include "helper.h" } /* Writeback SR_F transaltion-space to execution-space. */ diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 2da7bc7..45ec840 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -175,10 +175,6 @@ void ppc_translate_init(void) cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUPPCState, access_type), "access_type"); - /* register helpers */ -#define GEN_HELPER 2 -#include "helper.h" - done_init = 1; } diff --git a/target-s390x/translate.c b/target-s390x/translate.c index afe90eb..bc99a37 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -188,10 +188,6 @@ void s390x_translate_init(void) offsetof(CPUS390XState, fregs[i].d), cpu_reg_names[i + 16]); } - - /* register helpers */ -#define GEN_HELPER 2 -#include "helper.h" } static TCGv_i64 load_reg(int reg) diff --git a/target-sh4/translate.c b/target-sh4/translate.c index c06b29f..2272eb0 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -143,10 +143,6 @@ void sh4_translate_init(void) offsetof(CPUSH4State, fregs[i]), fregnames[i]); - /* register helpers */ -#define GEN_HELPER 2 -#include "helper.h" - done_init = 1; } diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 36615f1..dce64c3 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -5456,11 +5456,6 @@ void gen_intermediate_code_init(CPUSPARCState *env) offsetof(CPUSPARCState, fpr[i]), fregnames[i]); } - - /* register helpers */ - -#define GEN_HELPER 2 -#include "helper.h" } } diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 1246895..4572890 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -74,9 +74,6 @@ void uc32_translate_init(void) cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUUniCore32State, regs[i]), regnames[i]); } - -#define GEN_HELPER 2 -#include "helper.h" } static int num_temps; diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 24343bd..06641bb 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -238,8 +238,6 @@ void xtensa_translate_init(void) uregnames[i].name); } } -#define GEN_HELPER 2 -#include "helper.h" } static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt) diff --git a/tcg/tcg.c b/tcg/tcg.c index 98b1c37..59251c0 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -254,6 +254,8 @@ void tcg_pool_reset(TCGContext *s) s->pool_current = NULL; } +#include "helper.h" + void tcg_context_init(TCGContext *s) { int op, total_args, n; @@ -284,7 +286,11 @@ void tcg_context_init(TCGContext *s) sorted_args += n; args_ct += n; } - + + /* Register helpers. */ +#define GEN_HELPER 2 +#include "helper.h" + tcg_target_init(s); }