From patchwork Sat Sep 14 21:54:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 274960 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 6D4CB2C012E for ; Sun, 15 Sep 2013 07:59:14 +1000 (EST) Received: from localhost ([::1]:54690 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VKxs0-0007Zk-7R for incoming@patchwork.ozlabs.org; Sat, 14 Sep 2013 17:59:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34523) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VKxo6-00017Z-To for qemu-devel@nongnu.org; Sat, 14 Sep 2013 17:55:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VKxo0-0003ya-VO for qemu-devel@nongnu.org; Sat, 14 Sep 2013 17:55:10 -0400 Received: from mail-pd0-x230.google.com ([2607:f8b0:400e:c02::230]:61397) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VKxo0-0003w4-LV for qemu-devel@nongnu.org; Sat, 14 Sep 2013 17:55:04 -0400 Received: by mail-pd0-f176.google.com with SMTP id q10so2606589pdj.7 for ; Sat, 14 Sep 2013 14:55:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=YpUkU6XBTIEq6ioxNqI559uJQV7GZaCki6j+Kz+WX20=; b=h1MYt00iykr409ZBL+zLy5phgoXru+4kjHDQrXqzt3bCsRL4Lwc8UVTvCJICwW1j6I 6TS2J+Pp1IrVB06m/i+SeqvKoGLsRJbQyRYakUydQcYDBP+mtS2nG9aCO/KA5YUItZey NvM1UThseQOWS8kQAu3AEiMAtBk4mGAyZ6K3jed96RB9AQ2c0l7ZNTsbQTwYp/OysvK+ HgArIrh7mAKArVwOfdcLMIffFpQfeyaPv6v/r5bVe5ftD/peYVX33p6u6jrKkUbn31cG tdzmU+J58Hiyit5xpt+5h+ORY6sM/qZeIPrBXGGUYSVd+frwxpfHpsamBjNQ30qywPJw k1JQ== X-Received: by 10.68.202.38 with SMTP id kf6mr5602801pbc.43.1379195703696; Sat, 14 Sep 2013 14:55:03 -0700 (PDT) Received: from pebble.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. 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X-Received-From: 2607:f8b0:400e:c02::230 Cc: peter.maydell@linaro.org, claudio.fontana@gmail.com Subject: [Qemu-devel] [PATCH v4 06/33] tcg-aarch64: Merge enum aarch64_srr_opc with AArch64Insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org And since we're no longer talking about opcodes, merge the 0x1ac02000 data2 primary opcode with the shift subcode to create the full insn. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 49 ++++++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 25 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 99d9884..be6d05a 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -216,14 +216,13 @@ typedef enum { INSN_ADDS = 0x2b000000, INSN_SUB = 0x4b000000, INSN_SUBS = 0x6b000000, -} AArch64Insn; -enum aarch64_srr_opc { - SRR_SHL = 0x0, - SRR_SHR = 0x4, - SRR_SAR = 0x8, - SRR_ROR = 0xc -}; + /* Data-processing (2 source) instructions */ + INSN_LSLV = 0x1ac02000, + INSN_LSRV = 0x1ac02400, + INSN_ASRV = 0x1ac02800, + INSN_RORV = 0x1ac02c00, +} AArch64Insn; static inline enum aarch64_ldst_op_data aarch64_ldst_get_data(TCGOpcode tcg_op) @@ -472,12 +471,12 @@ static inline void tcg_out_mul(TCGContext *s, TCGType ext, } static inline void tcg_out_shiftrot_reg(TCGContext *s, - enum aarch64_srr_opc opc, TCGType ext, + AArch64Insn insn, TCGType ext, TCGReg rd, TCGReg rn, TCGReg rm) { /* using 2-source data processing instructions 0x1ac02000 */ - unsigned int base = ext ? 0x9ac02000 : 0x1ac02000; - tcg_out32(s, base | rm << 16 | opc << 8 | rn << 5 | rd); + unsigned int base = insn | (ext ? 0x80000000 : 0); + tcg_out32(s, base | rm << 16 | rn << 5 | rd); } static inline void tcg_out_ubfm(TCGContext *s, TCGType ext, TCGReg rd, @@ -1214,47 +1213,47 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_shl_i64: case INDEX_op_shl_i32: - if (c2) { /* LSL / UBFM Wd, Wn, (32 - m) */ + if (c2) { tcg_out_shl(s, ext, a0, a1, a2); - } else { /* LSL / LSLV */ - tcg_out_shiftrot_reg(s, SRR_SHL, ext, a0, a1, a2); + } else { + tcg_out_shiftrot_reg(s, INSN_LSLV, ext, a0, a1, a2); } break; case INDEX_op_shr_i64: case INDEX_op_shr_i32: - if (c2) { /* LSR / UBFM Wd, Wn, m, 31 */ + if (c2) { tcg_out_shr(s, ext, a0, a1, a2); - } else { /* LSR / LSRV */ - tcg_out_shiftrot_reg(s, SRR_SHR, ext, a0, a1, a2); + } else { + tcg_out_shiftrot_reg(s, INSN_LSRV, ext, a0, a1, a2); } break; case INDEX_op_sar_i64: case INDEX_op_sar_i32: - if (c2) { /* ASR / SBFM Wd, Wn, m, 31 */ + if (c2) { tcg_out_sar(s, ext, a0, a1, a2); - } else { /* ASR / ASRV */ - tcg_out_shiftrot_reg(s, SRR_SAR, ext, a0, a1, a2); + } else { + tcg_out_shiftrot_reg(s, INSN_ASRV, ext, a0, a1, a2); } break; case INDEX_op_rotr_i64: case INDEX_op_rotr_i32: - if (c2) { /* ROR / EXTR Wd, Wm, Wm, m */ + if (c2) { tcg_out_rotr(s, ext, a0, a1, a2); - } else { /* ROR / RORV */ - tcg_out_shiftrot_reg(s, SRR_ROR, ext, a0, a1, a2); + } else { + tcg_out_shiftrot_reg(s, INSN_RORV, ext, a0, a1, a2); } break; case INDEX_op_rotl_i64: - case INDEX_op_rotl_i32: /* same as rotate right by (32 - m) */ - if (c2) { /* ROR / EXTR Wd, Wm, Wm, 32 - m */ + case INDEX_op_rotl_i32: + if (c2) { tcg_out_rotl(s, ext, a0, a1, a2); } else { tcg_out_arith(s, INSN_SUB, 0, TCG_REG_TMP, TCG_REG_XZR, a2, 0); - tcg_out_shiftrot_reg(s, SRR_ROR, ext, a0, a1, TCG_REG_TMP); + tcg_out_shiftrot_reg(s, INSN_RORV, ext, a0, a1, TCG_REG_TMP); } break;