From patchwork Wed Sep 11 14:37:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 274318 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 6B5672C00E7 for ; Thu, 12 Sep 2013 01:10:55 +1000 (EST) Received: from localhost ([::1]:36305 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VJlcM-000210-Gh for incoming@patchwork.ozlabs.org; Wed, 11 Sep 2013 10:42:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34525) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VJlYO-0005e4-F7 for qemu-devel@nongnu.org; Wed, 11 Sep 2013 10:38:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VJlYG-0005dp-TP for qemu-devel@nongnu.org; Wed, 11 Sep 2013 10:38:00 -0400 Received: from cantor2.suse.de ([195.135.220.15]:45114 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VJlYG-0005ci-AU for qemu-devel@nongnu.org; Wed, 11 Sep 2013 10:37:52 -0400 Received: from relay1.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 8F702A5211; Wed, 11 Sep 2013 16:37:51 +0200 (CEST) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Wed, 11 Sep 2013 16:37:23 +0200 Message-Id: <1378910260-7688-8-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1378910260-7688-1-git-send-email-afaerber@suse.de> References: <1378910260-7688-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 195.135.220.15 Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [Qemu-devel] [PATCH v4 07/24] a9mpcore: Embed ARMMPTimerState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Andreas Färber Prepares for QOM realize. Signed-off-by: Andreas Färber --- hw/cpu/a9mpcore.c | 29 ++++++++++++++--------- hw/timer/arm_mptimer.c | 35 ++++----------------------- include/hw/timer/arm_mptimer.h | 54 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 76 insertions(+), 42 deletions(-) create mode 100644 include/hw/timer/arm_mptimer.h diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index df92e3f..db3907e 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -11,6 +11,7 @@ #include "hw/sysbus.h" #include "hw/intc/arm_gic.h" #include "hw/misc/a9scu.h" +#include "hw/timer/arm_mptimer.h" #define TYPE_A9MPCORE_PRIV "a9mpcore_priv" #define A9MPCORE_PRIV(obj) \ @@ -23,12 +24,12 @@ typedef struct A9MPPrivState { uint32_t num_cpu; MemoryRegion container; - DeviceState *mptimer; - DeviceState *wdt; uint32_t num_irq; GICState gic; A9SCUState scu; + ARMMPTimerState mptimer; + ARMMPTimerState wdt; } A9MPPrivState; static void a9mp_priv_set_irq(void *opaque, int irq, int level) @@ -50,12 +51,18 @@ static void a9mp_priv_initfn(Object *obj) object_initialize(&s->scu, sizeof(s->scu), TYPE_A9_SCU); qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); + + object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER); + qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default()); + + object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ARM_MPTIMER); + qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default()); } static int a9mp_priv_init(SysBusDevice *dev) { A9MPPrivState *s = A9MPCORE_PRIV(dev); - DeviceState *gicdev, *scudev; + DeviceState *gicdev, *scudev, *mptimerdev, *wdtdev; SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev; int i; @@ -76,15 +83,15 @@ static int a9mp_priv_init(SysBusDevice *dev) qdev_init_nofail(scudev); scubusdev = SYS_BUS_DEVICE(&s->scu); - s->mptimer = qdev_create(NULL, "arm_mptimer"); - qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu); - qdev_init_nofail(s->mptimer); - timerbusdev = SYS_BUS_DEVICE(s->mptimer); + mptimerdev = DEVICE(&s->mptimer); + qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); + qdev_init_nofail(mptimerdev); + timerbusdev = SYS_BUS_DEVICE(&s->mptimer); - s->wdt = qdev_create(NULL, "arm_mptimer"); - qdev_prop_set_uint32(s->wdt, "num-cpu", s->num_cpu); - qdev_init_nofail(s->wdt); - wdtbusdev = SYS_BUS_DEVICE(s->wdt); + wdtdev = DEVICE(&s->wdt); + qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu); + qdev_init_nofail(wdtdev); + wdtbusdev = SYS_BUS_DEVICE(&s->wdt); /* Memory map (addresses are offsets from PERIPHBASE): * 0x0000-0x00ff -- Snoop Control Unit diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index 2853db4..d9f9494 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -19,7 +19,7 @@ * with this program; if not, see . */ -#include "hw/sysbus.h" +#include "hw/timer/arm_mptimer.h" #include "qemu/timer.h" #include "qom/cpu.h" @@ -27,34 +27,6 @@ * which is used in both the ARM11MPCore and Cortex-A9MP. */ -#define MAX_CPUS 4 - -/* State of a single timer or watchdog block */ -typedef struct { - uint32_t count; - uint32_t load; - uint32_t control; - uint32_t status; - int64_t tick; - QEMUTimer *timer; - qemu_irq irq; - MemoryRegion iomem; -} TimerBlock; - -#define TYPE_ARM_MPTIMER "arm_mptimer" -#define ARM_MPTIMER(obj) \ - OBJECT_CHECK(ARMMPTimerState, (obj), TYPE_ARM_MPTIMER) - -typedef struct { - /*< private >*/ - SysBusDevice parent_obj; - /*< public >*/ - - uint32_t num_cpu; - TimerBlock timerblock[MAX_CPUS]; - MemoryRegion iomem; -} ARMMPTimerState; - static inline int get_current_cpu(ARMMPTimerState *s) { if (current_cpu->cpu_index >= s->num_cpu) { @@ -240,8 +212,9 @@ static void arm_mptimer_realize(DeviceState *dev, Error **errp) ARMMPTimerState *s = ARM_MPTIMER(dev); int i; - if (s->num_cpu < 1 || s->num_cpu > MAX_CPUS) { - hw_error("%s: num-cpu must be between 1 and %d\n", __func__, MAX_CPUS); + if (s->num_cpu < 1 || s->num_cpu > ARM_MPTIMER_MAX_CPUS) { + hw_error("%s: num-cpu must be between 1 and %d\n", + __func__, ARM_MPTIMER_MAX_CPUS); } /* We implement one timer block per CPU, and expose multiple MMIO regions: * * region 0 is "timer for this core" diff --git a/include/hw/timer/arm_mptimer.h b/include/hw/timer/arm_mptimer.h new file mode 100644 index 0000000..b34cba0 --- /dev/null +++ b/include/hw/timer/arm_mptimer.h @@ -0,0 +1,54 @@ +/* + * Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP + * + * Copyright (c) 2006-2007 CodeSourcery. + * Copyright (c) 2011 Linaro Limited + * Written by Paul Brook, Peter Maydell + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ +#ifndef HW_TIMER_ARM_MPTIMER_H +#define HW_TIMER_ARM_MPTIMER_H + +#include "hw/sysbus.h" + +#define ARM_MPTIMER_MAX_CPUS 4 + +/* State of a single timer or watchdog block */ +typedef struct { + uint32_t count; + uint32_t load; + uint32_t control; + uint32_t status; + int64_t tick; + QEMUTimer *timer; + qemu_irq irq; + MemoryRegion iomem; +} TimerBlock; + +#define TYPE_ARM_MPTIMER "arm_mptimer" +#define ARM_MPTIMER(obj) \ + OBJECT_CHECK(ARMMPTimerState, (obj), TYPE_ARM_MPTIMER) + +typedef struct { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + uint32_t num_cpu; + TimerBlock timerblock[ARM_MPTIMER_MAX_CPUS]; + MemoryRegion iomem; +} ARMMPTimerState; + +#endif