From patchwork Tue Sep 10 18:52:02 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 273998 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D06382C0123 for ; Wed, 11 Sep 2013 05:05:27 +1000 (EST) Received: from localhost ([::1]:59641 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VJTFd-0005k4-Sx for incoming@patchwork.ozlabs.org; Tue, 10 Sep 2013 15:05:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51882) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VJT3E-0004oh-9A for qemu-devel@nongnu.org; Tue, 10 Sep 2013 14:52:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VJT39-0005M5-0h for qemu-devel@nongnu.org; Tue, 10 Sep 2013 14:52:36 -0400 Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1d0::1]:43712 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VJT38-0005Dk-97 for qemu-devel@nongnu.org; Tue, 10 Sep 2013 14:52:30 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1VJT30-00021a-Gh; Tue, 10 Sep 2013 19:52:22 +0100 From: Peter Maydell To: Anthony Liguori Date: Tue, 10 Sep 2013 19:52:02 +0100 Message-Id: <1378839142-7726-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1378839142-7726-1-git-send-email-peter.maydell@linaro.org> References: <1378839142-7726-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Cc: qemu-devel@nongnu.org Subject: [Qemu-devel] [PULL 08/28] target-arm: Abstract out load/store from a vaddr in AArch32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org AArch32 code (ie traditional 32 bit world) expects to be able to pass a vaddr in a TCGv_i32. However when QEMU is compiled with TARGET_LONG_BITS=32 the TCG load/store functions take a TCGv_i64. Abstract out load/store with a 32 bit vaddr so we have a place to put the zero extension of the vaddr and the extension/truncation of the data value. Apart from the function definitions most of this patch is a simple s/tcg_gen_qemu_/gen_aa32_/. Signed-off-by: Peter Maydell Message-id: 1378235544-22290-3-git-send-email-peter.maydell@linaro.org --- target-arm/translate.c | 334 ++++++++++++++++++++++++++++++------------------ 1 file changed, 210 insertions(+), 124 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 8bcfaf3..ad499b6 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -843,6 +843,90 @@ static inline void store_reg_from_load(CPUARMState *env, DisasContext *s, } } +/* Abstractions of "generate code to do a guest load/store for + * AArch32", where a vaddr is always 32 bits (and is zero + * extended if we're a 64 bit core) and data is also + * 32 bits unless specifically doing a 64 bit access. + * These functions work like tcg_gen_qemu_{ld,st}* except + * that their arguments are TCGv_i32 rather than TCGv. + */ +#if TARGET_LONG_BITS == 32 + +#define DO_GEN_LD(OP) \ +static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \ +{ \ + tcg_gen_qemu_##OP(val, addr, index); \ +} + +#define DO_GEN_ST(OP) \ +static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \ +{ \ + tcg_gen_qemu_##OP(val, addr, index); \ +} + +static inline void gen_aa32_ld64(TCGv_i64 val, TCGv_i32 addr, int index) +{ + tcg_gen_qemu_ld64(val, addr, index); +} + +static inline void gen_aa32_st64(TCGv_i64 val, TCGv_i32 addr, int index) +{ + tcg_gen_qemu_st64(val, addr, index); +} + +#else + +#define DO_GEN_LD(OP) \ +static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \ +{ \ + TCGv addr64 = tcg_temp_new(); \ + TCGv val64 = tcg_temp_new(); \ + tcg_gen_extu_i32_i64(addr64, addr); \ + tcg_gen_qemu_##OP(val64, addr64, index); \ + tcg_temp_free(addr64); \ + tcg_gen_trunc_i64_i32(val, val64); \ + tcg_temp_free(val64); \ +} + +#define DO_GEN_ST(OP) \ +static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \ +{ \ + TCGv addr64 = tcg_temp_new(); \ + TCGv val64 = tcg_temp_new(); \ + tcg_gen_extu_i32_i64(addr64, addr); \ + tcg_gen_extu_i32_i64(val64, val); \ + tcg_gen_qemu_##OP(val64, addr64, index); \ + tcg_temp_free(addr64); \ + tcg_temp_free(val64); \ +} + +static inline void gen_aa32_ld64(TCGv_i64 val, TCGv_i32 addr, int index) +{ + TCGv addr64 = tcg_temp_new(); + tcg_gen_extu_i32_i64(addr64, addr); + tcg_gen_qemu_ld64(val, addr64, index); + tcg_temp_free(addr64); +} + +static inline void gen_aa32_st64(TCGv_i64 val, TCGv_i32 addr, int index) +{ + TCGv addr64 = tcg_temp_new(); + tcg_gen_extu_i32_i64(addr64, addr); + tcg_gen_qemu_st64(val, addr64, index); + tcg_temp_free(addr64); +} + +#endif + +DO_GEN_LD(ld8s) +DO_GEN_LD(ld8u) +DO_GEN_LD(ld16s) +DO_GEN_LD(ld16u) +DO_GEN_LD(ld32u) +DO_GEN_ST(st8) +DO_GEN_ST(st16) +DO_GEN_ST(st32) + static inline void gen_set_pc_im(uint32_t val) { tcg_gen_movi_i32(cpu_R[15], val); @@ -1072,18 +1156,20 @@ VFP_GEN_FIX(ulto) static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv_i32 addr) { - if (dp) - tcg_gen_qemu_ld64(cpu_F0d, addr, IS_USER(s)); - else - tcg_gen_qemu_ld32u(cpu_F0s, addr, IS_USER(s)); + if (dp) { + gen_aa32_ld64(cpu_F0d, addr, IS_USER(s)); + } else { + gen_aa32_ld32u(cpu_F0s, addr, IS_USER(s)); + } } static inline void gen_vfp_st(DisasContext *s, int dp, TCGv_i32 addr) { - if (dp) - tcg_gen_qemu_st64(cpu_F0d, addr, IS_USER(s)); - else - tcg_gen_qemu_st32(cpu_F0s, addr, IS_USER(s)); + if (dp) { + gen_aa32_st64(cpu_F0d, addr, IS_USER(s)); + } else { + gen_aa32_st32(cpu_F0s, addr, IS_USER(s)); + } } static inline long @@ -1420,24 +1506,24 @@ static int disas_iwmmxt_insn(CPUARMState *env, DisasContext *s, uint32_t insn) if (insn & ARM_CP_RW_BIT) { if ((insn >> 28) == 0xf) { /* WLDRW wCx */ tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); iwmmxt_store_creg(wrd, tmp); } else { i = 1; if (insn & (1 << 8)) { if (insn & (1 << 22)) { /* WLDRD */ - tcg_gen_qemu_ld64(cpu_M0, addr, IS_USER(s)); + gen_aa32_ld64(cpu_M0, addr, IS_USER(s)); i = 0; } else { /* WLDRW wRd */ tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); } } else { tmp = tcg_temp_new_i32(); if (insn & (1 << 22)) { /* WLDRH */ - tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s)); + gen_aa32_ld16u(tmp, addr, IS_USER(s)); } else { /* WLDRB */ - tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s)); + gen_aa32_ld8u(tmp, addr, IS_USER(s)); } } if (i) { @@ -1449,24 +1535,24 @@ static int disas_iwmmxt_insn(CPUARMState *env, DisasContext *s, uint32_t insn) } else { if ((insn >> 28) == 0xf) { /* WSTRW wCx */ tmp = iwmmxt_load_creg(wrd); - tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + gen_aa32_st32(tmp, addr, IS_USER(s)); } else { gen_op_iwmmxt_movq_M0_wRn(wrd); tmp = tcg_temp_new_i32(); if (insn & (1 << 8)) { if (insn & (1 << 22)) { /* WSTRD */ - tcg_gen_qemu_st64(cpu_M0, addr, IS_USER(s)); + gen_aa32_st64(cpu_M0, addr, IS_USER(s)); } else { /* WSTRW wRd */ tcg_gen_trunc_i64_i32(tmp, cpu_M0); - tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + gen_aa32_st32(tmp, addr, IS_USER(s)); } } else { if (insn & (1 << 22)) { /* WSTRH */ tcg_gen_trunc_i64_i32(tmp, cpu_M0); - tcg_gen_qemu_st16(tmp, addr, IS_USER(s)); + gen_aa32_st16(tmp, addr, IS_USER(s)); } else { /* WSTRB */ tcg_gen_trunc_i64_i32(tmp, cpu_M0); - tcg_gen_qemu_st8(tmp, addr, IS_USER(s)); + gen_aa32_st8(tmp, addr, IS_USER(s)); } } } @@ -2531,15 +2617,15 @@ static TCGv_i32 gen_load_and_replicate(DisasContext *s, TCGv_i32 addr, int size) TCGv_i32 tmp = tcg_temp_new_i32(); switch (size) { case 0: - tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s)); + gen_aa32_ld8u(tmp, addr, IS_USER(s)); gen_neon_dup_u8(tmp, 0); break; case 1: - tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s)); + gen_aa32_ld16u(tmp, addr, IS_USER(s)); gen_neon_dup_low16(tmp); break; case 2: - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); break; default: /* Avoid compiler warnings. */ abort(); @@ -3817,11 +3903,11 @@ static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn) if (size == 3) { tmp64 = tcg_temp_new_i64(); if (load) { - tcg_gen_qemu_ld64(tmp64, addr, IS_USER(s)); + gen_aa32_ld64(tmp64, addr, IS_USER(s)); neon_store_reg64(tmp64, rd); } else { neon_load_reg64(tmp64, rd); - tcg_gen_qemu_st64(tmp64, addr, IS_USER(s)); + gen_aa32_st64(tmp64, addr, IS_USER(s)); } tcg_temp_free_i64(tmp64); tcg_gen_addi_i32(addr, addr, stride); @@ -3830,21 +3916,21 @@ static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn) if (size == 2) { if (load) { tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); neon_store_reg(rd, pass, tmp); } else { tmp = neon_load_reg(rd, pass); - tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + gen_aa32_st32(tmp, addr, IS_USER(s)); tcg_temp_free_i32(tmp); } tcg_gen_addi_i32(addr, addr, stride); } else if (size == 1) { if (load) { tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s)); + gen_aa32_ld16u(tmp, addr, IS_USER(s)); tcg_gen_addi_i32(addr, addr, stride); tmp2 = tcg_temp_new_i32(); - tcg_gen_qemu_ld16u(tmp2, addr, IS_USER(s)); + gen_aa32_ld16u(tmp2, addr, IS_USER(s)); tcg_gen_addi_i32(addr, addr, stride); tcg_gen_shli_i32(tmp2, tmp2, 16); tcg_gen_or_i32(tmp, tmp, tmp2); @@ -3854,10 +3940,10 @@ static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn) tmp = neon_load_reg(rd, pass); tmp2 = tcg_temp_new_i32(); tcg_gen_shri_i32(tmp2, tmp, 16); - tcg_gen_qemu_st16(tmp, addr, IS_USER(s)); + gen_aa32_st16(tmp, addr, IS_USER(s)); tcg_temp_free_i32(tmp); tcg_gen_addi_i32(addr, addr, stride); - tcg_gen_qemu_st16(tmp2, addr, IS_USER(s)); + gen_aa32_st16(tmp2, addr, IS_USER(s)); tcg_temp_free_i32(tmp2); tcg_gen_addi_i32(addr, addr, stride); } @@ -3866,7 +3952,7 @@ static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn) TCGV_UNUSED_I32(tmp2); for (n = 0; n < 4; n++) { tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s)); + gen_aa32_ld8u(tmp, addr, IS_USER(s)); tcg_gen_addi_i32(addr, addr, stride); if (n == 0) { tmp2 = tmp; @@ -3886,7 +3972,7 @@ static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn) } else { tcg_gen_shri_i32(tmp, tmp2, n * 8); } - tcg_gen_qemu_st8(tmp, addr, IS_USER(s)); + gen_aa32_st8(tmp, addr, IS_USER(s)); tcg_temp_free_i32(tmp); tcg_gen_addi_i32(addr, addr, stride); } @@ -4010,13 +4096,13 @@ static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn) tmp = tcg_temp_new_i32(); switch (size) { case 0: - tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s)); + gen_aa32_ld8u(tmp, addr, IS_USER(s)); break; case 1: - tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s)); + gen_aa32_ld16u(tmp, addr, IS_USER(s)); break; case 2: - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); break; default: /* Avoid compiler warnings. */ abort(); @@ -4034,13 +4120,13 @@ static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn) tcg_gen_shri_i32(tmp, tmp, shift); switch (size) { case 0: - tcg_gen_qemu_st8(tmp, addr, IS_USER(s)); + gen_aa32_st8(tmp, addr, IS_USER(s)); break; case 1: - tcg_gen_qemu_st16(tmp, addr, IS_USER(s)); + gen_aa32_st16(tmp, addr, IS_USER(s)); break; case 2: - tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + gen_aa32_st32(tmp, addr, IS_USER(s)); break; } tcg_temp_free_i32(tmp); @@ -6464,14 +6550,14 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, switch (size) { case 0: - tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s)); + gen_aa32_ld8u(tmp, addr, IS_USER(s)); break; case 1: - tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s)); + gen_aa32_ld16u(tmp, addr, IS_USER(s)); break; case 2: case 3: - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); break; default: abort(); @@ -6482,7 +6568,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, TCGv_i32 tmp2 = tcg_temp_new_i32(); tcg_gen_addi_i32(tmp2, addr, 4); tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp, tmp2, IS_USER(s)); + gen_aa32_ld32u(tmp, tmp2, IS_USER(s)); tcg_temp_free_i32(tmp2); tcg_gen_mov_i32(cpu_exclusive_high, tmp); store_reg(s, rt2, tmp); @@ -6524,14 +6610,14 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, tmp = tcg_temp_new_i32(); switch (size) { case 0: - tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s)); + gen_aa32_ld8u(tmp, addr, IS_USER(s)); break; case 1: - tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s)); + gen_aa32_ld16u(tmp, addr, IS_USER(s)); break; case 2: case 3: - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); break; default: abort(); @@ -6542,7 +6628,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, TCGv_i32 tmp2 = tcg_temp_new_i32(); tcg_gen_addi_i32(tmp2, addr, 4); tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp, tmp2, IS_USER(s)); + gen_aa32_ld32u(tmp, tmp2, IS_USER(s)); tcg_temp_free_i32(tmp2); tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label); tcg_temp_free_i32(tmp); @@ -6550,14 +6636,14 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, tmp = load_reg(s, rt); switch (size) { case 0: - tcg_gen_qemu_st8(tmp, addr, IS_USER(s)); + gen_aa32_st8(tmp, addr, IS_USER(s)); break; case 1: - tcg_gen_qemu_st16(tmp, addr, IS_USER(s)); + gen_aa32_st16(tmp, addr, IS_USER(s)); break; case 2: case 3: - tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + gen_aa32_st32(tmp, addr, IS_USER(s)); break; default: abort(); @@ -6566,7 +6652,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, if (size == 3) { tcg_gen_addi_i32(addr, addr, 4); tmp = load_reg(s, rt2); - tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + gen_aa32_st32(tmp, addr, IS_USER(s)); tcg_temp_free_i32(tmp); } tcg_gen_movi_i32(cpu_R[rd], 0); @@ -6613,11 +6699,11 @@ static void gen_srs(DisasContext *s, } tcg_gen_addi_i32(addr, addr, offset); tmp = load_reg(s, 14); - tcg_gen_qemu_st32(tmp, addr, 0); + gen_aa32_st32(tmp, addr, 0); tcg_temp_free_i32(tmp); tmp = load_cpu_field(spsr); tcg_gen_addi_i32(addr, addr, 4); - tcg_gen_qemu_st32(tmp, addr, 0); + gen_aa32_st32(tmp, addr, 0); tcg_temp_free_i32(tmp); if (writeback) { switch (amode) { @@ -6763,10 +6849,10 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) tcg_gen_addi_i32(addr, addr, offset); /* Load PC into tmp and CPSR into tmp2. */ tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp, addr, 0); + gen_aa32_ld32u(tmp, addr, 0); tcg_gen_addi_i32(addr, addr, 4); tmp2 = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp2, addr, 0); + gen_aa32_ld32u(tmp2, addr, 0); if (insn & (1 << 21)) { /* Base writeback. */ switch (i) { @@ -7322,13 +7408,13 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) tmp = tcg_temp_new_i32(); switch (op1) { case 0: /* lda */ - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); break; case 2: /* ldab */ - tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s)); + gen_aa32_ld8u(tmp, addr, IS_USER(s)); break; case 3: /* ldah */ - tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s)); + gen_aa32_ld16u(tmp, addr, IS_USER(s)); break; default: abort(); @@ -7339,13 +7425,13 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) tmp = load_reg(s, rm); switch (op1) { case 0: /* stl */ - tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + gen_aa32_st32(tmp, addr, IS_USER(s)); break; case 2: /* stlb */ - tcg_gen_qemu_st8(tmp, addr, IS_USER(s)); + gen_aa32_st8(tmp, addr, IS_USER(s)); break; case 3: /* stlh */ - tcg_gen_qemu_st16(tmp, addr, IS_USER(s)); + gen_aa32_st16(tmp, addr, IS_USER(s)); break; default: abort(); @@ -7400,11 +7486,11 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) tmp = load_reg(s, rm); tmp2 = tcg_temp_new_i32(); if (insn & (1 << 22)) { - tcg_gen_qemu_ld8u(tmp2, addr, IS_USER(s)); - tcg_gen_qemu_st8(tmp, addr, IS_USER(s)); + gen_aa32_ld8u(tmp2, addr, IS_USER(s)); + gen_aa32_st8(tmp, addr, IS_USER(s)); } else { - tcg_gen_qemu_ld32u(tmp2, addr, IS_USER(s)); - tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp2, addr, IS_USER(s)); + gen_aa32_st32(tmp, addr, IS_USER(s)); } tcg_temp_free_i32(tmp); tcg_temp_free_i32(addr); @@ -7426,14 +7512,14 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) tmp = tcg_temp_new_i32(); switch(sh) { case 1: - tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s)); + gen_aa32_ld16u(tmp, addr, IS_USER(s)); break; case 2: - tcg_gen_qemu_ld8s(tmp, addr, IS_USER(s)); + gen_aa32_ld8s(tmp, addr, IS_USER(s)); break; default: case 3: - tcg_gen_qemu_ld16s(tmp, addr, IS_USER(s)); + gen_aa32_ld16s(tmp, addr, IS_USER(s)); break; } load = 1; @@ -7443,21 +7529,21 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) if (sh & 1) { /* store */ tmp = load_reg(s, rd); - tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + gen_aa32_st32(tmp, addr, IS_USER(s)); tcg_temp_free_i32(tmp); tcg_gen_addi_i32(addr, addr, 4); tmp = load_reg(s, rd + 1); - tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + gen_aa32_st32(tmp, addr, IS_USER(s)); tcg_temp_free_i32(tmp); load = 0; } else { /* load */ tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); store_reg(s, rd, tmp); tcg_gen_addi_i32(addr, addr, 4); tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); rd++; load = 1; } @@ -7465,7 +7551,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) } else { /* store */ tmp = load_reg(s, rd); - tcg_gen_qemu_st16(tmp, addr, IS_USER(s)); + gen_aa32_st16(tmp, addr, IS_USER(s)); tcg_temp_free_i32(tmp); load = 0; } @@ -7798,17 +7884,17 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) /* load */ tmp = tcg_temp_new_i32(); if (insn & (1 << 22)) { - tcg_gen_qemu_ld8u(tmp, tmp2, i); + gen_aa32_ld8u(tmp, tmp2, i); } else { - tcg_gen_qemu_ld32u(tmp, tmp2, i); + gen_aa32_ld32u(tmp, tmp2, i); } } else { /* store */ tmp = load_reg(s, rd); if (insn & (1 << 22)) { - tcg_gen_qemu_st8(tmp, tmp2, i); + gen_aa32_st8(tmp, tmp2, i); } else { - tcg_gen_qemu_st32(tmp, tmp2, i); + gen_aa32_st32(tmp, tmp2, i); } tcg_temp_free_i32(tmp); } @@ -7875,7 +7961,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) if (insn & (1 << 20)) { /* load */ tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); if (user) { tmp2 = tcg_const_i32(i); gen_helper_set_user_reg(cpu_env, tmp2, tmp); @@ -7902,7 +7988,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) } else { tmp = load_reg(s, i); } - tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + gen_aa32_st32(tmp, addr, IS_USER(s)); tcg_temp_free_i32(tmp); } j++; @@ -8161,20 +8247,20 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw if (insn & (1 << 20)) { /* ldrd */ tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); store_reg(s, rs, tmp); tcg_gen_addi_i32(addr, addr, 4); tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); store_reg(s, rd, tmp); } else { /* strd */ tmp = load_reg(s, rs); - tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + gen_aa32_st32(tmp, addr, IS_USER(s)); tcg_temp_free_i32(tmp); tcg_gen_addi_i32(addr, addr, 4); tmp = load_reg(s, rd); - tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + gen_aa32_st32(tmp, addr, IS_USER(s)); tcg_temp_free_i32(tmp); } if (insn & (1 << 21)) { @@ -8212,11 +8298,11 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw tcg_gen_add_i32(addr, addr, tmp); tcg_temp_free_i32(tmp); tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s)); + gen_aa32_ld16u(tmp, addr, IS_USER(s)); } else { /* tbb */ tcg_temp_free_i32(tmp); tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s)); + gen_aa32_ld8u(tmp, addr, IS_USER(s)); } tcg_temp_free_i32(addr); tcg_gen_shli_i32(tmp, tmp, 1); @@ -8253,13 +8339,13 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw tmp = tcg_temp_new_i32(); switch (op) { case 0: /* ldab */ - tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s)); + gen_aa32_ld8u(tmp, addr, IS_USER(s)); break; case 1: /* ldah */ - tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s)); + gen_aa32_ld16u(tmp, addr, IS_USER(s)); break; case 2: /* lda */ - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); break; default: abort(); @@ -8269,13 +8355,13 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw tmp = load_reg(s, rs); switch (op) { case 0: /* stlb */ - tcg_gen_qemu_st8(tmp, addr, IS_USER(s)); + gen_aa32_st8(tmp, addr, IS_USER(s)); break; case 1: /* stlh */ - tcg_gen_qemu_st16(tmp, addr, IS_USER(s)); + gen_aa32_st16(tmp, addr, IS_USER(s)); break; case 2: /* stl */ - tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + gen_aa32_st32(tmp, addr, IS_USER(s)); break; default: abort(); @@ -8303,10 +8389,10 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw tcg_gen_addi_i32(addr, addr, -8); /* Load PC into tmp and CPSR into tmp2. */ tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp, addr, 0); + gen_aa32_ld32u(tmp, addr, 0); tcg_gen_addi_i32(addr, addr, 4); tmp2 = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp2, addr, 0); + gen_aa32_ld32u(tmp2, addr, 0); if (insn & (1 << 21)) { /* Base writeback. */ if (insn & (1 << 24)) { @@ -8345,7 +8431,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw if (insn & (1 << 20)) { /* Load. */ tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); if (i == 15) { gen_bx(s, tmp); } else if (i == rn) { @@ -8357,7 +8443,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw } else { /* Store. */ tmp = load_reg(s, i); - tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + gen_aa32_st32(tmp, addr, IS_USER(s)); tcg_temp_free_i32(tmp); } tcg_gen_addi_i32(addr, addr, 4); @@ -9135,19 +9221,19 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw tmp = tcg_temp_new_i32(); switch (op) { case 0: - tcg_gen_qemu_ld8u(tmp, addr, user); + gen_aa32_ld8u(tmp, addr, user); break; case 4: - tcg_gen_qemu_ld8s(tmp, addr, user); + gen_aa32_ld8s(tmp, addr, user); break; case 1: - tcg_gen_qemu_ld16u(tmp, addr, user); + gen_aa32_ld16u(tmp, addr, user); break; case 5: - tcg_gen_qemu_ld16s(tmp, addr, user); + gen_aa32_ld16s(tmp, addr, user); break; case 2: - tcg_gen_qemu_ld32u(tmp, addr, user); + gen_aa32_ld32u(tmp, addr, user); break; default: tcg_temp_free_i32(tmp); @@ -9164,13 +9250,13 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw tmp = load_reg(s, rs); switch (op) { case 0: - tcg_gen_qemu_st8(tmp, addr, user); + gen_aa32_st8(tmp, addr, user); break; case 1: - tcg_gen_qemu_st16(tmp, addr, user); + gen_aa32_st16(tmp, addr, user); break; case 2: - tcg_gen_qemu_st32(tmp, addr, user); + gen_aa32_st32(tmp, addr, user); break; default: tcg_temp_free_i32(tmp); @@ -9307,7 +9393,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) addr = tcg_temp_new_i32(); tcg_gen_movi_i32(addr, val); tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); tcg_temp_free_i32(addr); store_reg(s, rd, tmp); break; @@ -9510,28 +9596,28 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) switch (op) { case 0: /* str */ - tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + gen_aa32_st32(tmp, addr, IS_USER(s)); break; case 1: /* strh */ - tcg_gen_qemu_st16(tmp, addr, IS_USER(s)); + gen_aa32_st16(tmp, addr, IS_USER(s)); break; case 2: /* strb */ - tcg_gen_qemu_st8(tmp, addr, IS_USER(s)); + gen_aa32_st8(tmp, addr, IS_USER(s)); break; case 3: /* ldrsb */ - tcg_gen_qemu_ld8s(tmp, addr, IS_USER(s)); + gen_aa32_ld8s(tmp, addr, IS_USER(s)); break; case 4: /* ldr */ - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); break; case 5: /* ldrh */ - tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s)); + gen_aa32_ld16u(tmp, addr, IS_USER(s)); break; case 6: /* ldrb */ - tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s)); + gen_aa32_ld8u(tmp, addr, IS_USER(s)); break; case 7: /* ldrsh */ - tcg_gen_qemu_ld16s(tmp, addr, IS_USER(s)); + gen_aa32_ld16s(tmp, addr, IS_USER(s)); break; } if (op >= 3) { /* load */ @@ -9553,12 +9639,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) if (insn & (1 << 11)) { /* load */ tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); store_reg(s, rd, tmp); } else { /* store */ tmp = load_reg(s, rd); - tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + gen_aa32_st32(tmp, addr, IS_USER(s)); tcg_temp_free_i32(tmp); } tcg_temp_free_i32(addr); @@ -9575,12 +9661,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) if (insn & (1 << 11)) { /* load */ tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s)); + gen_aa32_ld8u(tmp, addr, IS_USER(s)); store_reg(s, rd, tmp); } else { /* store */ tmp = load_reg(s, rd); - tcg_gen_qemu_st8(tmp, addr, IS_USER(s)); + gen_aa32_st8(tmp, addr, IS_USER(s)); tcg_temp_free_i32(tmp); } tcg_temp_free_i32(addr); @@ -9597,12 +9683,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) if (insn & (1 << 11)) { /* load */ tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s)); + gen_aa32_ld16u(tmp, addr, IS_USER(s)); store_reg(s, rd, tmp); } else { /* store */ tmp = load_reg(s, rd); - tcg_gen_qemu_st16(tmp, addr, IS_USER(s)); + gen_aa32_st16(tmp, addr, IS_USER(s)); tcg_temp_free_i32(tmp); } tcg_temp_free_i32(addr); @@ -9618,12 +9704,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) if (insn & (1 << 11)) { /* load */ tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); store_reg(s, rd, tmp); } else { /* store */ tmp = load_reg(s, rd); - tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + gen_aa32_st32(tmp, addr, IS_USER(s)); tcg_temp_free_i32(tmp); } tcg_temp_free_i32(addr); @@ -9691,12 +9777,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) if (insn & (1 << 11)) { /* pop */ tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); store_reg(s, i, tmp); } else { /* push */ tmp = load_reg(s, i); - tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + gen_aa32_st32(tmp, addr, IS_USER(s)); tcg_temp_free_i32(tmp); } /* advance to the next address. */ @@ -9708,13 +9794,13 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) if (insn & (1 << 11)) { /* pop pc */ tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); /* don't set the pc until the rest of the instruction has completed */ } else { /* push lr */ tmp = load_reg(s, 14); - tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + gen_aa32_st32(tmp, addr, IS_USER(s)); tcg_temp_free_i32(tmp); } tcg_gen_addi_i32(addr, addr, 4); @@ -9840,7 +9926,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) if (insn & (1 << 11)) { /* load */ tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); + gen_aa32_ld32u(tmp, addr, IS_USER(s)); if (i == rn) { loaded_var = tmp; } else { @@ -9849,7 +9935,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) } else { /* store */ tmp = load_reg(s, i); - tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + gen_aa32_st32(tmp, addr, IS_USER(s)); tcg_temp_free_i32(tmp); } /* advance to the next address */