diff mbox

[v2,4/4] tcg/optimize: add known-zero bits compute for load ops

Message ID 1378747670-25512-5-git-send-email-aurelien@aurel32.net
State New
Headers show

Commit Message

Aurelien Jarno Sept. 9, 2013, 5:27 p.m. UTC 
Cc: Richard Henderson <rth@twiddle.net>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 tcg/optimize.c |   13 +++++++++++++
 1 file changed, 13 insertions(+)

Comments

Richard Henderson Dec. 6, 2013, 5:53 p.m. UTC | #1 
On 09/10/2013 05:27 AM, Aurelien Jarno wrote:
> +        CASE_OP_32_64(ld8u):
> +        case INDEX_op_qemu_ld8u:
> +            mask = 0xff;
> +            break;
> +        CASE_OP_32_64(ld16u):
> +        case INDEX_op_qemu_ld16u:
> +            mask = 0xffff;
> +            break;
> +        case INDEX_op_ld32u_i64:
> +        case INDEX_op_qemu_ld32u:
> +            mask = 0xffffffffu;
> +            break;
> +

This could stand to be updated for the new INDEX_op_qemu_ld_{i32,i64} opcodes,
where you have to look at args[last] to find out the width and sign.

But this is still an improvement for the old opcodes.

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~
diff mbox

Patch

diff --git a/tcg/optimize.c b/tcg/optimize.c
index b1f736b..044f456 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -787,6 +787,19 @@  static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr,
             mask = temps[args[3]].mask | temps[args[4]].mask;
             break;
 
+        CASE_OP_32_64(ld8u):
+        case INDEX_op_qemu_ld8u:
+            mask = 0xff;
+            break;
+        CASE_OP_32_64(ld16u):
+        case INDEX_op_qemu_ld16u:
+            mask = 0xffff;
+            break;
+        case INDEX_op_ld32u_i64:
+        case INDEX_op_qemu_ld32u:
+            mask = 0xffffffffu;
+            break;
+
         default:
             break;
         }