[RFC,1/6] make.rule: fix $(obj) to a real relative path

Makefile.target includes rule.mak and unnested common-obj-y, then prefix
them with '../', this will ignore object specific QEMU_CFLAGS in subdir
Makefile.objs:

    $(obj)/curl.o: QEMU_CFLAGS += $(CURL_CFLAGS)

Because $(obj) here is './block', instead of '../block'. This doesn't
hurt compiling because we basically build all .o from top Makefile,
before entering Makefile.target, but it will affact arriving per-object
libs support.

The starting point of $(obj) is fixed before including ./Makefile.objs,
to get consistency with nested Makefile rules in target rule and
variable definition.

Signed-off-by: Fam Zheng <famz@redhat.com>
---
 Makefile.target | 3 ++-
 rules.mak       | 6 +++---
 2 files changed, 5 insertions(+), 4 deletions(-)

Il 05/09/2013 12:20, Fam Zheng ha scritto:
> Makefile.target includes rule.mak and unnested common-obj-y, then prefix
> them with '../', this will ignore object specific QEMU_CFLAGS in subdir
> Makefile.objs:
> 
>     $(obj)/curl.o: QEMU_CFLAGS += $(CURL_CFLAGS)
> 
> Because $(obj) here is './block', instead of '../block'. This doesn't
> hurt compiling because we basically build all .o from top Makefile,
> before entering Makefile.target, but it will affact arriving per-object
> libs support.
> 
> The starting point of $(obj) is fixed before including ./Makefile.objs,
> to get consistency with nested Makefile rules in target rule and
> variable definition.
> 
> Signed-off-by: Fam Zheng <famz@redhat.com>
> ---
>  Makefile.target | 3 ++-
>  rules.mak       | 6 +++---
>  2 files changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/Makefile.target b/Makefile.target
> index 9a49852..b35e7c1 100644
> --- a/Makefile.target
> +++ b/Makefile.target
> @@ -144,12 +144,13 @@ endif # CONFIG_SOFTMMU
>  %/translate.o: QEMU_CFLAGS += $(TRANSLATE_OPT_CFLAGS)
>  
>  nested-vars += obj-y
> +obj := ..
>  
>  # This resolves all nested paths, so it must come last
>  include $(SRC_PATH)/Makefile.objs
>  
>  all-obj-y = $(obj-y)
> -all-obj-y += $(addprefix ../, $(common-obj-y))
> +all-obj-y += $(addprefix $(obj)/, $(common-obj-y))

The bug is clearly there, but I'm not sure this is correct.

"obj" is the path to the object file.  obj-y files are built in the
target directory, thus the extra ".." should apply only to common-obj-y;
$(obj-y) should not be prefixed.  So perhaps you need to:

1) move the nested-vars and unnest-vars call from Makefile.objs to
Makefile.  also move this line:

   QEMU_CFLAGS+=$(GLIB_CFLAGS)

which has no business in Makefile.objs.  With this change, Makefile.objs
is just a list, like other */Makefile.objs files.

2) remove the additional complication where common-obj-y is including
block-obj-y, just add it to all-obj-y manually.

3) in Makefile.target, do this:

block-obj-y = ../
common-obj-y = ../
nested-vars = obj-y block-obj-y common-obj-y
dummy := $(call unnest-vars)
all-obj-y = $(obj-y) $(common-obj-y) $(block-obj-y)

(Can all be done in a single patch).

?

>  
>  ifndef CONFIG_HAIKU
>  LIBS+=-lm
> diff --git a/rules.mak b/rules.mak
> index 4499745..5758137 100644
> --- a/rules.mak
> +++ b/rules.mak
> @@ -103,7 +103,6 @@ clean: clean-timestamp
>  
>  # magic to descend into other directories
>  
> -obj := .
>  old-nested-dirs :=
>  
>  define push-var
> @@ -119,9 +118,10 @@ endef
>  
>  define unnest-dir
>  $(foreach var,$(nested-vars),$(call push-var,$(var),$1/))
> -$(eval obj := $(obj)/$1)
> +$(eval old-obj := $(obj))
> +$(eval obj := $(if $(obj),$(obj)/$1,$1))
>  $(eval include $(SRC_PATH)/$1/Makefile.objs)
> -$(eval obj := $(patsubst %/$1,%,$(obj)))
> +$(eval obj := $(old-obj))
>  $(foreach var,$(nested-vars),$(call pop-var,$(var),$1/))

old-obj doesn't work if you have multiple levels of nesting.  But you
can call the variable something like obj-parent-$1 instead to solve this
problem.

However, please clean it up afterwards with "$(eval obj-parent-$1 := )".

Paolo

>  endef
>  
>