From patchwork Tue Sep 3 16:06:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 272287 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0E2F52C00A8 for ; Wed, 4 Sep 2013 02:07:14 +1000 (EST) Received: from localhost ([::1]:47284 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGt8J-0003ij-SD for incoming@patchwork.ozlabs.org; Tue, 03 Sep 2013 12:07:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52798) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGt7p-0003gP-9C for qemu-devel@nongnu.org; Tue, 03 Sep 2013 12:06:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VGt7j-0006n6-Tb for qemu-devel@nongnu.org; Tue, 03 Sep 2013 12:06:41 -0400 Received: from cantor2.suse.de ([195.135.220.15]:43531 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGt7j-0006mv-ND for qemu-devel@nongnu.org; Tue, 03 Sep 2013 12:06:35 -0400 Received: from relay1.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 4D4DDA52D9; Tue, 3 Sep 2013 18:06:35 +0200 (CEST) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2013 18:06:24 +0200 Message-Id: <1378224387-18760-2-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1378224387-18760-1-git-send-email-afaerber@suse.de> References: <1378224387-18760-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 195.135.220.15 Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [Qemu-devel] [PULL 1/4] a15mpcore: Use qemu_get_cpu() for generic timers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This simplifies the loop and aids with refactoring of CPU list. Requested-by: Peter Maydell Signed-off-by: Andreas Färber --- hw/cpu/a15mpcore.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index af182da..9abba67 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -50,7 +50,6 @@ static int a15mp_priv_init(SysBusDevice *dev) SysBusDevice *busdev; const char *gictype = "arm_gic"; int i; - CPUState *cpu; if (kvm_irqchip_in_kernel()) { gictype = "kvm-arm-gic"; @@ -72,8 +71,8 @@ static int a15mp_priv_init(SysBusDevice *dev) /* Wire the outputs from each CPU's generic timer to the * appropriate GIC PPI inputs */ - for (i = 0, cpu = first_cpu; i < s->num_cpu; i++, cpu = cpu->next_cpu) { - DeviceState *cpudev = DEVICE(cpu); + for (i = 0; i < s->num_cpu; i++) { + DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); int ppibase = s->num_irq - 32 + i * 32; /* physical timer; we wire it up to the non-secure timer's ID, * since a real A15 always has TrustZone but QEMU doesn't.