From patchwork Mon Sep 2 17:54:57 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 272039 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 859012C0095 for ; Tue, 3 Sep 2013 04:20:05 +1000 (EST) Received: from localhost ([::1]:41459 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGYWG-0002qF-GV for incoming@patchwork.ozlabs.org; Mon, 02 Sep 2013 14:06:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56834) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGYLy-0006EX-7T for qemu-devel@nongnu.org; Mon, 02 Sep 2013 13:56:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VGYLs-0001Dp-CH for qemu-devel@nongnu.org; Mon, 02 Sep 2013 13:55:54 -0400 Received: from mail-pb0-x22b.google.com ([2607:f8b0:400e:c01::22b]:43672) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGYLr-0001Dd-Oo for qemu-devel@nongnu.org; Mon, 02 Sep 2013 13:55:48 -0400 Received: by mail-pb0-f43.google.com with SMTP id md4so4984867pbc.2 for ; Mon, 02 Sep 2013 10:55:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=FQsA4aL+0GggCt9ADRtwnNoect2EWkx+QBFWCE8x+PA=; b=ZMNi+OM6AOlHt6Yi8iMShxv68Y87gFvmUKeGH6fdb3MUtPq9R7zoFQ+qraki9sC9+F Jqv2eXd/XiHsX2hqbKrUeEvPh+dKh72+rTlAAcgfpoFoXaE60g95yRVDp+qSTi6I8PWm J2BTqShzIyvgtilC7goEQk552TMjIGF2gzv/2kj0zPPH4gEaXWDKJbYETTlIQyFttNCX MdYUfnS4jh4TQjtmyyo5KolB2h/Bw9qALj0XjUbvEchjTOwK5SIUjvPEVA84btdatB27 o2FPRiKQJL0MVGzo+iPKMni7l5XPT5N+CsBZAjgCQ+kkvYQfpo4iFRhhnQpai+FoDbOk cIZw== X-Received: by 10.66.25.232 with SMTP id f8mr27996654pag.25.1378144546747; Mon, 02 Sep 2013 10:55:46 -0700 (PDT) Received: from pebble.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPSA id tr10sm17218114pbc.22.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 02 Sep 2013 10:55:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 2 Sep 2013 10:54:57 -0700 Message-Id: <1378144503-15808-24-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1378144503-15808-1-git-send-email-rth@twiddle.net> References: <1378144503-15808-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c01::22b Cc: claudio.fontana@huawei.com, Richard Henderson Subject: [Qemu-devel] [PATCH v3 23/29] tcg-aarch64: Pass return address to load/store helpers directly. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 18 ------------------ tcg/aarch64/tcg-target.c | 44 ++++++++++++++++++++++++++------------------ 2 files changed, 26 insertions(+), 36 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 7510246..9a3ec05 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -320,24 +320,6 @@ extern uintptr_t tci_tb_ptr; #define GETPC() (GETRA() - GETPC_ADJ) -/* The LDST optimizations splits code generation into fast and slow path. - In some implementations, we pass the "logical" return address manually; - in others, we must infer the logical return from the true return. */ -#if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU) -# if defined(__aarch64__) -# define GETRA_LDST(RA) tcg_getra_ldst(RA) -static inline uintptr_t tcg_getra_ldst(uintptr_t ra) -{ - int32_t b; - ra += 4; /* skip one instruction */ - b = *(int32_t *)ra; /* load the branch insn */ - b = (b << 6) >> (6 - 2); /* extract the displacement */ - ra += b; /* apply the displacement */ - return ra; -} -# endif -#endif /* CONFIG_QEMU_LDST_OPTIMIZATION */ - /* ??? Delete these once they are no longer used. */ bool is_tcg_gen_code(uintptr_t pc_ptr); #ifdef GETRA_LDST diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index be74d2b..1d0db02 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -968,39 +968,46 @@ static inline void tcg_out_addsub2(TCGContext *s, int ext, TCGReg rl, } } -static inline void tcg_out_nop(TCGContext *s) -{ - tcg_out32(s, 0xd503201f); -} - #ifdef CONFIG_SOFTMMU -/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, - int mmu_idx) */ +/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, + * int mmu_idx, uintptr_t ra) + */ static const void * const qemu_ld_helpers[4] = { - helper_ldb_mmu, - helper_ldw_mmu, - helper_ldl_mmu, - helper_ldq_mmu, + helper_ret_ldub_mmu, + helper_ret_lduw_mmu, + helper_ret_ldul_mmu, + helper_ret_ldq_mmu, }; -/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr, - uintxx_t val, int mmu_idx) */ +/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, + * uintxx_t val, int mmu_idx, uintptr_t ra) + */ static const void * const qemu_st_helpers[4] = { - helper_stb_mmu, - helper_stw_mmu, - helper_stl_mmu, - helper_stq_mmu, + helper_ret_stb_mmu, + helper_ret_stw_mmu, + helper_ret_stl_mmu, + helper_ret_stq_mmu, }; +static inline void tcg_out_adr(TCGContext *s, TCGReg rd, tcg_target_long addr) +{ + addr -= (tcg_target_long)s->code_ptr; + assert(addr == sextract64(addr, 0, 21)); + tcg_fmt_Rd_disp21(s, INSN_ADR, rd, addr); +} + static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { reloc_pc19(lb->label_ptr[0], (tcg_target_long)s->code_ptr); tcg_out_movr(s, 1, TCG_REG_X0, TCG_AREG0); tcg_out_movr(s, (TARGET_LONG_BITS == 64), TCG_REG_X1, lb->addrlo_reg); tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, lb->mem_index); + tcg_out_adr(s, TCG_REG_X3, (uintptr_t)lb->raddr); + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (tcg_target_long)qemu_ld_helpers[lb->opc & 3]); tcg_out_callr(s, TCG_REG_TMP); + if (lb->opc & 0x04) { tcg_out_sxt(s, 1, lb->opc & 3, lb->datalo_reg, TCG_REG_X0); } else { @@ -1018,11 +1025,12 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) tcg_out_movr(s, (TARGET_LONG_BITS == 64), TCG_REG_X1, lb->addrlo_reg); tcg_out_movr(s, 1, TCG_REG_X2, lb->datalo_reg); tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, lb->mem_index); + tcg_out_adr(s, TCG_REG_X4, (uintptr_t)lb->raddr); + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (tcg_target_long)qemu_st_helpers[lb->opc & 3]); tcg_out_callr(s, TCG_REG_TMP); - tcg_out_nop(s); tcg_out_goto(s, (tcg_target_long)lb->raddr); }