From patchwork Fri Aug 30 17:47:17 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 271390 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A42652C00CA for ; Sat, 31 Aug 2013 03:52:43 +1000 (EST) Received: from localhost ([::1]:51870 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VFSsD-0003dP-UB for incoming@patchwork.ozlabs.org; Fri, 30 Aug 2013 13:52:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40918) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VFSnT-0005Z4-Ll for qemu-devel@nongnu.org; Fri, 30 Aug 2013 13:47:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VFSnN-0007H2-N5 for qemu-devel@nongnu.org; Fri, 30 Aug 2013 13:47:47 -0400 Received: from mail-pd0-x235.google.com ([2607:f8b0:400e:c02::235]:44678) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VFSnN-0007Gv-FD for qemu-devel@nongnu.org; Fri, 30 Aug 2013 13:47:41 -0400 Received: by mail-pd0-f181.google.com with SMTP id g10so2146951pdj.26 for ; Fri, 30 Aug 2013 10:47:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=GS9fr9G49IpMiwQePu2t+pOtMcl2DDJHz2Y9bX6WOqI=; b=kwMvqbykTmZADGJO3Af3NURs7pU3srIh5d2mnwmYzrCweB2zvIQlUgGAXl2z4vsZdP vtjhawG5IWxvm2B2AAuM/XKtaavuPrC6At7bGUcbjT9GGi5ce2p87aEXKJozaa6rgNIR IEDgYLPqMswVNsRhg/cvuguvAEPV9XdD4NH/J4NLvHr5/FbojVsV9twJMz77SA0KhDos H0uNSVO8vYSEc2ncrjuf64aU71eNc+Bw/+8pQ3/7wiE0mF9HlAcspOlGzzvXSP07cOLb atrlB87SDTv8XkKNOaDyaxIvjw9J8ceE/QudwR94qv+bb6sE9Py4a+ko+NGYNMl/9YJr Yn0g== X-Received: by 10.66.175.133 with SMTP id ca5mr12316945pac.40.1377884860520; Fri, 30 Aug 2013 10:47:40 -0700 (PDT) Received: from fremont.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPSA id bg3sm45701777pbb.44.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 30 Aug 2013 10:47:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 30 Aug 2013 10:47:17 -0700 Message-Id: <1377884837-6581-9-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1377884837-6581-1-git-send-email-rth@twiddle.net> References: <1377884837-6581-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c02::235 Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v2 8/8] tcg-arm: Move the tlb addend load earlier X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org There are free scheduling slots between the sequence of comparison instructions. This requires changing the register in use to avoid conflict with those compares. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index ff331a1..bc50d54 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -1182,8 +1182,8 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, * add r2, r2, r0, lsl #CPU_TLB_ENTRY_BITS (3) * ldr r0, [r2, #cmp] (4) * tst addr_reg, #s_mask - * cmpeq r0, tmp, lsl #TARGET_PAGE_BITS (5) - * ldr r1, [r2, #add] + * ldr r1, [r2, #add] (5) + * cmpeq r0, tmp, lsl #TARGET_PAGE_BITS */ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, addrlo, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); @@ -1220,6 +1220,9 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, 0, addrlo, (1 << s_bits) - 1); } + /* Load the tlb addend. */ + tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R2, add_off); + tcg_out_dat_reg(s, (s_bits ? COND_EQ : COND_AL), ARITH_CMP, 0, TCG_REG_R0, TCG_REG_TMP, SHIFT_IMM_LSL(TARGET_PAGE_BITS)); @@ -1228,9 +1231,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, TCG_REG_R1, addrhi, SHIFT_IMM_LSL(0)); } - /* Load the tlb addend. */ - tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R2, add_off); - return TCG_REG_R1; + return TCG_REG_R2; } /* Record the context of a call to the out of line helper code for the slow