From patchwork Mon Aug 5 16:35:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 264708 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1A9202C0082 for ; Tue, 6 Aug 2013 02:37:11 +1000 (EST) Received: from localhost ([::1]:42856 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6NmK-0001WV-9o for incoming@patchwork.ozlabs.org; Mon, 05 Aug 2013 12:37:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44101) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6Nm0-0001Vn-IU for qemu-devel@nongnu.org; Mon, 05 Aug 2013 12:36:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V6Nlv-00073t-8y for qemu-devel@nongnu.org; Mon, 05 Aug 2013 12:36:44 -0400 Received: from multi.imgtec.com ([194.200.65.239]:48407) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6Nlv-00073X-2K for qemu-devel@nongnu.org; Mon, 05 Aug 2013 12:36:39 -0400 From: Leon Alrae To: Date: Mon, 5 Aug 2013 17:35:26 +0100 Message-ID: <1375720526-59566-1-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.5.4 MIME-Version: 1.0 X-Originating-IP: [192.168.14.85] X-SEF-Processed: 7_3_0_01192__2013_08_05_17_36_34 X-detected-operating-system: by eggs.gnu.org: Windows XP X-Received-From: 194.200.65.239 Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com, leon.alrae@imgtec.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v2] target-mips: fix decoding of microMIPS POOL32Axf instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Fix incorrect assumption that DSP and non-DSP versions of the following instructions have the same encoding: MULT, MULTU, MADD, MADDU, MSUB, MSUBU, MFHI, MFLO, MTHI, MTLO. Correct the existing (non-DSP) instructions and add DSP equivalents. Reference: MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set MIPS Architecture for Programmers Volume IV-e: The MIPS DSP Module for the microMIPS32 Architecture Signed-off-by: Leon Alrae --- target-mips/translate.c | 58 ++++++++++++++++++++++++++++++++++++++++++---- 1 files changed, 53 insertions(+), 5 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index c1d57a7..90394a0 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -11061,6 +11061,36 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs) } break; #endif + case 0x2a: + switch (minor & 3) { + case MADD_ACC: + gen_muldiv(ctx, OPC_MADD, (ctx->opcode >> 14) & 3, rs, rt); + break; + case MADDU_ACC: + gen_muldiv(ctx, OPC_MADDU, (ctx->opcode >> 14) & 3, rs, rt); + break; + case MSUB_ACC: + gen_muldiv(ctx, OPC_MSUB, (ctx->opcode >> 14) & 3, rs, rt); + break; + case MSUBU_ACC: + gen_muldiv(ctx, OPC_MSUBU, (ctx->opcode >> 14) & 3, rs, rt); + break; + default: + goto pool32axf_invalid; + } + break; + case 0x32: + switch (minor & 3) { + case MULT_ACC: + gen_muldiv(ctx, OPC_MULT, (ctx->opcode >> 14) & 3, rs, rt); + break; + case MULTU_ACC: + gen_muldiv(ctx, OPC_MULTU, (ctx->opcode >> 14) & 3, rs, rt); + break; + default: + goto pool32axf_invalid; + } + break; case 0x2c: switch (minor) { case SEB: @@ -11113,7 +11143,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs) mips32_op = OPC_MSUBU; do_mul: check_insn(ctx, ISA_MIPS32); - gen_muldiv(ctx, mips32_op, (ctx->opcode >> 14) & 3, rs, rt); + gen_muldiv(ctx, mips32_op, 0, rs, rt); break; default: goto pool32axf_invalid; @@ -11247,19 +11277,37 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs) goto pool32axf_invalid; } break; + case 0x01: + switch (minor & 3) { + case MFHI_ACC: + gen_HILO(ctx, OPC_MFHI, minor >> 2, rs); + break; + case MFLO_ACC: + gen_HILO(ctx, OPC_MFLO, minor >> 2, rs); + break; + case MTHI_ACC: + gen_HILO(ctx, OPC_MTHI, minor >> 2, rs); + break; + case MTLO_ACC: + gen_HILO(ctx, OPC_MTLO, minor >> 2, rs); + break; + default: + goto pool32axf_invalid; + } + break; case 0x35: switch (minor & 3) { case MFHI32: - gen_HILO(ctx, OPC_MFHI, minor >> 2, rs); + gen_HILO(ctx, OPC_MFHI, 0, rs); break; case MFLO32: - gen_HILO(ctx, OPC_MFLO, minor >> 2, rs); + gen_HILO(ctx, OPC_MFLO, 0, rs); break; case MTHI32: - gen_HILO(ctx, OPC_MTHI, minor >> 2, rs); + gen_HILO(ctx, OPC_MTHI, 0, rs); break; case MTLO32: - gen_HILO(ctx, OPC_MTLO, minor >> 2, rs); + gen_HILO(ctx, OPC_MTLO, 0, rs); break; default: goto pool32axf_invalid;