From patchwork Mon Jul 29 14:19:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Borntraeger X-Patchwork-Id: 262789 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id C26F92C00F3 for ; Tue, 30 Jul 2013 00:22:07 +1000 (EST) Received: from localhost ([::1]:59217 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V3oKr-0004DE-Gg for incoming@patchwork.ozlabs.org; Mon, 29 Jul 2013 10:22:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57996) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V3oIM-0000dZ-HF for qemu-devel@nongnu.org; Mon, 29 Jul 2013 10:19:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V3oIA-0000ni-DR for qemu-devel@nongnu.org; Mon, 29 Jul 2013 10:19:30 -0400 Received: from e06smtp14.uk.ibm.com ([195.75.94.110]:34518) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V3oIA-0000nA-57 for qemu-devel@nongnu.org; Mon, 29 Jul 2013 10:19:18 -0400 Received: from /spool/local by e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 29 Jul 2013 15:10:36 +0100 Received: from b06cxnps4075.portsmouth.uk.ibm.com (d06relay12.portsmouth.uk.ibm.com [9.149.109.197]) by d06dlp02.portsmouth.uk.ibm.com (Postfix) with ESMTP id 26639219005F for ; Mon, 29 Jul 2013 15:23:29 +0100 (BST) Received: from d06av12.portsmouth.uk.ibm.com (d06av12.portsmouth.uk.ibm.com [9.149.37.247]) by b06cxnps4075.portsmouth.uk.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r6TEJ2if66256910 for ; Mon, 29 Jul 2013 14:19:03 GMT Received: from d06av12.portsmouth.uk.ibm.com (localhost [127.0.0.1]) by d06av12.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id r6TEJDf9005593 for ; Mon, 29 Jul 2013 08:19:14 -0600 Received: from tuxmaker.boeblingen.de.ibm.com (tuxmaker.boeblingen.de.ibm.com [9.152.85.9]) by d06av12.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id r6TEJDU0005580; Mon, 29 Jul 2013 08:19:13 -0600 Received: by tuxmaker.boeblingen.de.ibm.com (Postfix, from userid 25651) id ABAF41224439; Mon, 29 Jul 2013 16:19:13 +0200 (CEST) From: Christian Borntraeger To: Alexander Graf Date: Mon, 29 Jul 2013 16:19:25 +0200 Message-Id: <1375107567-24301-5-git-send-email-borntraeger@de.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1375107567-24301-1-git-send-email-borntraeger@de.ibm.com> References: <1375107567-24301-1-git-send-email-borntraeger@de.ibm.com> X-TM-AS-MML: No X-Content-Scanned: Fidelis XPS MAILER x-cbid: 13072914-1948-0000-0000-000005D2CC12 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] X-Received-From: 195.75.94.110 Cc: Cornelia Huck , Christian Borntraeger , =?UTF-8?q?Andreas=20F=C3=A4rber?= , qemu-devel Subject: [Qemu-devel] [PATCH 4/6] s390/cpu: split CPU reset into architectured functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org s390 provides several CPU resets: - CPU reset, clears interrupts, stop processing, clears TLB, but does not touch registers - initial CPU reset, like CPU reset, but also clears PSW, prefix, FPC, timer and control registers. It does not touch gprs, fprs and acrs (!) - Power on reset: the full monty wire up CPUClass reset to the full monty, but provide the lesser resets as part of S390CPUClass. Signed-off-by: Christian Borntraeger --- target-s390x/cpu-qom.h | 4 ++++ target-s390x/cpu.c | 40 +++++++++++++++++++++++++++++++++------- 2 files changed, 37 insertions(+), 7 deletions(-) diff --git a/target-s390x/cpu-qom.h b/target-s390x/cpu-qom.h index 2dc1750..ac0460e 100644 --- a/target-s390x/cpu-qom.h +++ b/target-s390x/cpu-qom.h @@ -37,6 +37,8 @@ * @parent_realize: The parent class' realize handler. * @parent_reset: The parent class' reset handler. * @load_normal: Performs a load normal. + * @cpu_reset: Performs a CPU reset. + * @initial_cpu_reset: Performs an initial CPU reset. * * An S/390 CPU model. */ @@ -48,6 +50,8 @@ typedef struct S390CPUClass { DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); void (*load_normal)(CPUState *cpu); + void (*cpu_reset)(CPUState *cpu); + void (*initial_cpu_reset)(CPUState *cpu); } S390CPUClass; /** diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c index 0915c45..5fab918 100644 --- a/target-s390x/cpu.c +++ b/target-s390x/cpu.c @@ -74,7 +74,7 @@ static void s390_cpu_load_normal(CPUState *s) s390_add_running_cpu(cpu); } -/* CPUClass::reset() */ +/* S390CPUClass::cpu_reset() */ static void s390_cpu_reset(CPUState *s) { S390CPU *cpu = S390_CPU(s); @@ -85,11 +85,6 @@ static void s390_cpu_reset(CPUState *s) scc->parent_reset(s); - memset(env, 0, offsetof(CPUS390XState, breakpoints)); - - /* architectured initial values for CR 0 and 14 */ - env->cregs[0] = CR0_RESET; - env->cregs[14] = CR14_RESET; /* set halted to 1 to make sure we can add the cpu in * s390_ipl_cpu code, where CPUState::halted is set back to 0 * after incrementing the cpu counter */ @@ -108,6 +103,35 @@ static void s390_cpu_machine_reset_cb(void *opaque) } #endif +/* S390CPUClass::initial_reset() */ +static void s390_cpu_initial_reset(CPUState *s) +{ + S390CPU *cpu = S390_CPU(s); + CPUS390XState *env = &cpu->env; + + s390_cpu_reset(s); + /* initial reset does not touch regs,fregs and aregs */ + memset(&env->fpc, 0, offsetof(CPUS390XState, breakpoints) - + offsetof(CPUS390XState, fpc)); + + /* architectured initial values for CR 0 and 14 */ + env->cregs[0] = CR0_RESET; + env->cregs[14] = CR14_RESET; +} + +/* CPUClass:reset() */ +static void s390_cpu_full_reset(CPUState *s) +{ + S390CPU *cpu = S390_CPU(s); + CPUS390XState *env = &cpu->env; + + s390_cpu_initial_reset(s); + /* also reset regs,aregs and fregs */ + memset(env, 0, offsetof(CPUS390XState, fpc)); +} + + + static void s390_cpu_realizefn(DeviceState *dev, Error **errp) { S390CPU *cpu = S390_CPU(dev); @@ -178,7 +202,9 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) scc->parent_reset = cc->reset; scc->load_normal = s390_cpu_load_normal; - cc->reset = s390_cpu_reset; + scc->cpu_reset = s390_cpu_reset; + scc->initial_cpu_reset = s390_cpu_initial_reset; + cc->reset = s390_cpu_full_reset; cc->do_interrupt = s390_cpu_do_interrupt; cc->dump_state = s390_cpu_dump_state;