From patchwork Mon Jul 8 11:12:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arthur Chunqi Li X-Patchwork-Id: 257538 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 7079F2C02AB for ; Mon, 8 Jul 2013 21:13:18 +1000 (EST) Received: from localhost ([::1]:49892 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uw9Na-0001Ax-Cb for incoming@patchwork.ozlabs.org; Mon, 08 Jul 2013 07:13:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54633) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uw9NH-0001Aq-Dj for qemu-devel@nongnu.org; Mon, 08 Jul 2013 07:12:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Uw9ND-00063e-6R for qemu-devel@nongnu.org; Mon, 08 Jul 2013 07:12:55 -0400 Received: from mail-pb0-x22a.google.com ([2607:f8b0:400e:c01::22a]:41396) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uw9NC-00063Q-SV for qemu-devel@nongnu.org; Mon, 08 Jul 2013 07:12:51 -0400 Received: by mail-pb0-f42.google.com with SMTP id un1so4201257pbc.29 for ; Mon, 08 Jul 2013 04:12:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=h6ubRok+jSIZhL+E6q3Xy2b/8pmogEp0kXW40RbPUJE=; b=Ty+GF0FiLpWlPMDb/pcb+YjR79rlA2p9ka+XdfbJdtHroBbyK41pW8AspySRtdW0vD KrBeWlTeAbQdmm8UKkfuz5TQt96fga7gNB/fEOJ0PfxrPAh8BXkx9SAwMcKDZsWIo5eN /H2T5li/cftwADla/XyAvykzviDjyQ3Ni+TR4o5I8PYgAg/SUAyWtLZXNb3FpmnpqLQx KBpwVNaEUIv960nRhCdVxcknMjNwdWAme7A4WAqKEsOc7Y29SpPiwoPZbEK11uLoYpe5 yu3/qMF5LwqPBGtw/SIX8mdc8DumY85D052cQ3d4aFZQc9ku5kXa+qKo1/HWtMGB2Uk/ xuWA== X-Received: by 10.66.164.199 with SMTP id ys7mr22677414pab.104.1373281970114; Mon, 08 Jul 2013 04:12:50 -0700 (PDT) Received: from Blade1-02.Blade1-02 ([162.105.146.101]) by mx.google.com with ESMTPSA id te9sm7483779pab.6.2013.07.08.04.12.45 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 08 Jul 2013 04:12:48 -0700 (PDT) From: Arthur Chunqi Li To: kvm@vger.kernel.org, qemu-devel@nongnu.org Date: Mon, 8 Jul 2013 19:12:35 +0800 Message-Id: <1373281955-17026-1-git-send-email-yzt356@gmail.com> X-Mailer: git-send-email 1.7.9.5 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c01::22a Cc: pbonzini@redhat.com, jan.kiszka@web.de, nyh@math.technion.ac.il, gleb@redhat.com, Arthur Chunqi Li Subject: [Qemu-devel] [PATCH v4] KVM: nVMX: Fix read/write to MSR_IA32_FEATURE_CONTROL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Nadav Har'El Fix read/write to IA32_FEATURE_CONTROL MSR in nested environment. This patch simulate this MSR in nested_vmx and the default value is 0x0. BIOS should set it to 0x5 before VMXON. After setting the lock bit, write to it will cause #GP(0). Another QEMU patch is also needed to handle emulation of reset and migration. Reset to vCPU should clear this MSR and migration should reserve value of it. This patch is based on Nadav's previous commit. http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/88478 Signed-off-by: Nadav Har'El Signed-off-by: Arthur Chunqi Li --- arch/x86/kvm/vmx.c | 35 +++++++++++++++++++++++++++++------ arch/x86/kvm/x86.c | 3 ++- 2 files changed, 31 insertions(+), 7 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index a7e1855..1200e4e 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -373,6 +373,7 @@ struct nested_vmx { * we must keep them pinned while L2 runs. */ struct page *apic_access_page; + u64 msr_ia32_feature_control; }; #define POSTED_INTR_ON 0 @@ -2282,8 +2283,11 @@ static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) switch (msr_index) { case MSR_IA32_FEATURE_CONTROL: - *pdata = 0; - break; + if (nested_vmx_allowed(vcpu)) { + *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control; + break; + } + return 0; case MSR_IA32_VMX_BASIC: /* * This MSR reports some information about VMX support. We @@ -2356,14 +2360,24 @@ static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) return 1; } -static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) +static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) { + u32 msr_index = msr_info->index; + u64 data = msr_info->data; + bool host_initialized = msr_info->host_initiated; + if (!nested_vmx_allowed(vcpu)) return 0; - if (msr_index == MSR_IA32_FEATURE_CONTROL) - /* TODO: the right thing. */ + if (msr_index == MSR_IA32_FEATURE_CONTROL) { + if (!host_initialized && + to_vmx(vcpu)->nested.msr_ia32_feature_control + & FEATURE_CONTROL_LOCKED) + return 0; + to_vmx(vcpu)->nested.msr_ia32_feature_control = data; return 1; + } + /* * No need to treat VMX capability MSRs specially: If we don't handle * them, handle_wrmsr will #GP(0), which is correct (they are readonly) @@ -2494,7 +2508,7 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) return 1; /* Otherwise falls through */ default: - if (vmx_set_vmx_msr(vcpu, msr_index, data)) + if (vmx_set_vmx_msr(vcpu, msr_info)) break; msr = find_msr_entry(vmx, msr_index); if (msr) { @@ -5576,6 +5590,8 @@ static int handle_vmon(struct kvm_vcpu *vcpu) struct kvm_segment cs; struct vcpu_vmx *vmx = to_vmx(vcpu); struct vmcs *shadow_vmcs; + const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED + | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; /* The Intel VMX Instruction Reference lists a bunch of bits that * are prerequisite to running VMXON, most notably cr4.VMXE must be @@ -5604,6 +5620,13 @@ static int handle_vmon(struct kvm_vcpu *vcpu) skip_emulated_instruction(vcpu); return 1; } + + if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES) + != VMXON_NEEDED_FEATURES) { + kvm_inject_gp(vcpu, 0); + return 1; + } + if (enable_shadow_vmcs) { shadow_vmcs = alloc_vmcs(); if (!shadow_vmcs) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index d21bce5..cff77c4 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -850,7 +850,8 @@ static u32 msrs_to_save[] = { #ifdef CONFIG_X86_64 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, #endif - MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA + MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, + MSR_IA32_FEATURE_CONTROL }; static unsigned num_msrs_to_save;