From patchwork Fri Jun 14 10:50:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 251351 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id EF50A2C008F for ; Fri, 14 Jun 2013 21:02:54 +1000 (EST) Received: from localhost ([::1]:57094 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UnRmP-0004C6-3o for incoming@patchwork.ozlabs.org; Fri, 14 Jun 2013 07:02:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56910) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UnRi3-0006LG-0T for qemu-devel@nongnu.org; Fri, 14 Jun 2013 06:58:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UnRi0-0006eO-D7 for qemu-devel@nongnu.org; Fri, 14 Jun 2013 06:58:22 -0400 Received: from isrv.corpit.ru ([86.62.121.231]:33574) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UnRi0-0006d5-3T; Fri, 14 Jun 2013 06:58:20 -0400 Received: from gandalf.tls.msk.ru (mjt.vpn.tls.msk.ru [192.168.177.99]) by isrv.corpit.ru (Postfix) with ESMTP id 5929841660; Fri, 14 Jun 2013 14:58:19 +0400 (MSK) Received: by gandalf.tls.msk.ru (Postfix, from userid 1000) id 56AC3529; Fri, 14 Jun 2013 14:50:48 +0400 (MSK) From: Michael Tokarev To: Anthony Liguori Date: Fri, 14 Jun 2013 14:50:42 +0400 Message-Id: <1371207042-17980-27-git-send-email-mjt@msgid.tls.msk.ru> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1371207042-17980-1-git-send-email-mjt@msgid.tls.msk.ru> References: <1371207042-17980-1-git-send-email-mjt@msgid.tls.msk.ru> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 86.62.121.231 Cc: qemu-trivial@nongnu.org, Hu Tao , Michael Tokarev , qemu-devel@nongnu.org Subject: [Qemu-devel] [PULL 26/26] piix: fix some printf errors when debug is enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Hu Tao And use PRIxxx macros if possible. Signed-off-by: Hu Tao Signed-off-by: Michael Tokarev --- hw/acpi/piix4.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index e6525ac..756df3b 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -518,7 +518,7 @@ static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) PIIX4PMState *s = opaque; uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); - PIIX4_DPRINTF("gpe read %x == %x\n", addr, val); + PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val); return val; } @@ -530,7 +530,7 @@ static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, acpi_gpe_ioport_writeb(&s->ar, addr, val); pm_update_sci(s); - PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); + PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); } static const MemoryRegionOps piix4_gpe_ops = { @@ -553,15 +553,15 @@ static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size) /* Manufacture an "up" value to cause a device check on any hotplug * slot with a device. Extra device checks are harmless. */ val = s->pci0_slot_device_present & s->pci0_hotplug_enable; - PIIX4_DPRINTF("pci_up_read %x\n", val); + PIIX4_DPRINTF("pci_up_read %" PRIu32 "\n", val); break; case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR: val = s->pci0_status.down; - PIIX4_DPRINTF("pci_down_read %x\n", val); + PIIX4_DPRINTF("pci_down_read %" PRIu32 "\n", val); break; case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: /* No feature defined yet */ - PIIX4_DPRINTF("pci_features_read %x\n", val); + PIIX4_DPRINTF("pci_features_read %" PRIu32 "\n", val); break; case PCI_RMV_BASE - PCI_HOTPLUG_ADDR: val = s->pci0_hotplug_enable; @@ -579,7 +579,7 @@ static void pci_write(void *opaque, hwaddr addr, uint64_t data, switch (addr) { case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: acpi_piix_eject_slot(opaque, (uint32_t)data); - PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== % " PRIu64 "\n", + PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, data); break; default: