From patchwork Thu May 30 17:53:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 247661 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (unknown [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0F4DF2C0085 for ; Fri, 31 May 2013 03:55:29 +1000 (EST) Received: from localhost ([::1]:41934 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ui74R-0006Ql-2e for incoming@patchwork.ozlabs.org; Thu, 30 May 2013 13:55:27 -0400 Received: from eggs.gnu.org ([208.118.235.92]:50160) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ui734-0004Jp-1V for qemu-devel@nongnu.org; Thu, 30 May 2013 13:54:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ui72v-0000ig-FA for qemu-devel@nongnu.org; Thu, 30 May 2013 13:54:01 -0400 Received: from mail-pd0-f176.google.com ([209.85.192.176]:40704) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ui72v-0000ic-8n for qemu-devel@nongnu.org; Thu, 30 May 2013 13:53:53 -0400 Received: by mail-pd0-f176.google.com with SMTP id r11so773900pdi.7 for ; Thu, 30 May 2013 10:53:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=rCXiEeSAMZrUMh3N+9BR4SeMv2RsHHgN99PGLdkH2Hc=; b=XUsH1N94VW8EHSP+HO9JZfzxSZtAvn1OusAsy1PrRfXkxCDfF8xkKETOS6JIKkDXIY 22lKc4LIvYfwBcz6Au2NDmChPUTXV085ENuFe/HUCcKsEHuvMtECJgi/ajdQbr2fCmNr +QpVODGv4low8DmAYkp7hZzH141ALi5Ap/EAF+4tEaYQXl9cgpK8ALZIYolL3P70xu7r Qex7ZcupTXnfhIb32GSGv/Uffhe1O77ZEH7Fp0tSDpXsw5UFO9jasYgB/9JP05s1k1wH XFo06rQkLEP2hconzZxleHP4XzuQ0EkMSB0OIxO4pGxU/uttX4eZY7SmWAz9Dc2okZ1E KgJA== X-Received: by 10.68.211.199 with SMTP id ne7mr8994131pbc.56.1369936432438; Thu, 30 May 2013 10:53:52 -0700 (PDT) Received: from fremont.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPSA id vv6sm45817120pab.6.2013.05.30.10.53.50 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 30 May 2013 10:53:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 30 May 2013 10:53:37 -0700 Message-Id: <1369936417-16522-4-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1369936417-16522-1-git-send-email-rth@twiddle.net> References: <1369936417-16522-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.176 Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 4/4] tcg-ppc64: Don't implement rem X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 26 -------------------------- tcg/ppc64/tcg-target.h | 4 ++-- 2 files changed, 2 insertions(+), 28 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 0fcf2b5..ea5f150 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -1616,18 +1616,6 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2])); break; - case INDEX_op_rem_i32: - tcg_out32 (s, DIVW | TAB (0, args[1], args[2])); - tcg_out32 (s, MULLW | TAB (0, 0, args[2])); - tcg_out32 (s, SUBF | TAB (args[0], 0, args[1])); - break; - - case INDEX_op_remu_i32: - tcg_out32 (s, DIVWU | TAB (0, args[1], args[2])); - tcg_out32 (s, MULLW | TAB (0, 0, args[2])); - tcg_out32 (s, SUBF | TAB (args[0], 0, args[1])); - break; - case INDEX_op_shl_i32: if (const_args[2]) { tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31 - args[2]); @@ -1785,16 +1773,6 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_divu_i64: tcg_out32 (s, DIVDU | TAB (args[0], args[1], args[2])); break; - case INDEX_op_rem_i64: - tcg_out32 (s, DIVD | TAB (0, args[1], args[2])); - tcg_out32 (s, MULLD | TAB (0, 0, args[2])); - tcg_out32 (s, SUBF | TAB (args[0], 0, args[1])); - break; - case INDEX_op_remu_i64: - tcg_out32 (s, DIVDU | TAB (0, args[1], args[2])); - tcg_out32 (s, MULLD | TAB (0, 0, args[2])); - tcg_out32 (s, SUBF | TAB (args[0], 0, args[1])); - break; case INDEX_op_qemu_ld8u: tcg_out_qemu_ld (s, args, 0); @@ -2065,8 +2043,6 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_mul_i32, { "r", "r", "rI" } }, { INDEX_op_div_i32, { "r", "r", "r" } }, { INDEX_op_divu_i32, { "r", "r", "r" } }, - { INDEX_op_rem_i32, { "r", "r", "r" } }, - { INDEX_op_remu_i32, { "r", "r", "r" } }, { INDEX_op_sub_i32, { "r", "rI", "ri" } }, { INDEX_op_and_i32, { "r", "r", "ri" } }, { INDEX_op_or_i32, { "r", "r", "ri" } }, @@ -2109,8 +2085,6 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_mul_i64, { "r", "r", "rI" } }, { INDEX_op_div_i64, { "r", "r", "r" } }, { INDEX_op_divu_i64, { "r", "r", "r" } }, - { INDEX_op_rem_i64, { "r", "r", "r" } }, - { INDEX_op_remu_i64, { "r", "r", "r" } }, { INDEX_op_neg_i64, { "r", "r" } }, { INDEX_op_not_i64, { "r", "r" } }, diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h index 7c600f1..48fc6e2 100644 --- a/tcg/ppc64/tcg-target.h +++ b/tcg/ppc64/tcg-target.h @@ -76,7 +76,7 @@ typedef enum { /* optional instructions */ #define TCG_TARGET_HAS_div_i32 1 -#define TCG_TARGET_HAS_rem_i32 1 +#define TCG_TARGET_HAS_rem_i32 0 #define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_ext8s_i32 1 #define TCG_TARGET_HAS_ext16s_i32 1 @@ -97,7 +97,7 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_div_i64 1 -#define TCG_TARGET_HAS_rem_i64 1 +#define TCG_TARGET_HAS_rem_i64 0 #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_ext8s_i64 1 #define TCG_TARGET_HAS_ext16s_i64 1