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[217.126.56.214]) by mx.google.com with ESMTPS id g6sm33990707qav.6.2013.04.15.11.44.38 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 15 Apr 2013 11:44:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 15 Apr 2013 20:41:01 +0200 Message-Id: <1366051272-12979-23-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1366051272-12979-1-git-send-email-rth@twiddle.net> References: <1366051272-12979-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.128.51 Cc: av1474@comtv.ru, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v5 22/33] tcg-ppc64: Handle constant inputs for some compound logicals X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Since we have special code to handle and/or/xor with a constant, apply the same to andc/orc/eqv with a constant. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 44 ++++++++++++++++++++++++++++++++++---------- 1 file changed, 34 insertions(+), 10 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index fb011e3..1cd2153 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -1394,17 +1394,19 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_and_i32: + a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { - tcg_out_andi32(s, args[0], args[1], args[2]); + tcg_out_andi32(s, a0, a1, a2); } else { - tcg_out32(s, AND | SAB(args[1], args[0], args[2])); + tcg_out32(s, AND | SAB(a1, a0, a2)); } break; case INDEX_op_and_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { - tcg_out_andi64(s, args[0], args[1], args[2]); + tcg_out_andi64(s, a0, a1, a2); } else { - tcg_out32(s, AND | SAB(args[1], args[0], args[2])); + tcg_out32(s, AND | SAB(a1, a0, a2)); } break; case INDEX_op_or_i64: @@ -1426,14 +1428,36 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, } break; case INDEX_op_andc_i32: + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + tcg_out_andi32(s, a0, a1, ~a2); + } else { + tcg_out32(s, ANDC | SAB(a1, a0, a2)); + } + break; case INDEX_op_andc_i64: - tcg_out32(s, ANDC | SAB(args[1], args[0], args[2])); + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + tcg_out_andi64(s, a0, a1, ~a2); + } else { + tcg_out32(s, ANDC | SAB(a1, a0, a2)); + } break; case INDEX_op_orc_i32: + if (const_args[2]) { + tcg_out_ori32(s, args[0], args[1], ~args[2]); + break; + } + /* FALLTHRU */ case INDEX_op_orc_i64: tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); break; case INDEX_op_eqv_i32: + if (const_args[2]) { + tcg_out_xori32(s, args[0], args[1], ~args[2]); + break; + } + /* FALLTHRU */ case INDEX_op_eqv_i64: tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); break; @@ -1820,9 +1844,9 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_and_i32, { "r", "r", "ri" } }, { INDEX_op_or_i32, { "r", "r", "ri" } }, { INDEX_op_xor_i32, { "r", "r", "ri" } }, - { INDEX_op_andc_i32, { "r", "r", "r" } }, - { INDEX_op_orc_i32, { "r", "r", "r" } }, - { INDEX_op_eqv_i32, { "r", "r", "r" } }, + { INDEX_op_andc_i32, { "r", "r", "ri" } }, + { INDEX_op_orc_i32, { "r", "r", "ri" } }, + { INDEX_op_eqv_i32, { "r", "r", "ri" } }, { INDEX_op_nand_i32, { "r", "r", "r" } }, { INDEX_op_nor_i32, { "r", "r", "r" } }, @@ -1840,10 +1864,10 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_add_i64, { "r", "r", "rT" } }, { INDEX_op_sub_i64, { "r", "rI", "rT" } }, - { INDEX_op_and_i64, { "r", "r", "rU" } }, + { INDEX_op_and_i64, { "r", "r", "ri" } }, { INDEX_op_or_i64, { "r", "r", "rU" } }, { INDEX_op_xor_i64, { "r", "r", "rU" } }, - { INDEX_op_andc_i64, { "r", "r", "r" } }, + { INDEX_op_andc_i64, { "r", "r", "ri" } }, { INDEX_op_orc_i64, { "r", "r", "r" } }, { INDEX_op_eqv_i64, { "r", "r", "r" } }, { INDEX_op_nand_i64, { "r", "r", "r" } },