From patchwork Thu Apr 4 22:56:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 233988 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id DA3092C008D for ; Fri, 5 Apr 2013 10:10:59 +1100 (EST) Received: from localhost ([::1]:34062 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNtJ3-0000gA-Kr for incoming@patchwork.ozlabs.org; Thu, 04 Apr 2013 19:10:57 -0400 Received: from eggs.gnu.org ([208.118.235.92]:47642) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNt66-0006HQ-7D for qemu-devel@nongnu.org; Thu, 04 Apr 2013 18:57:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UNt5x-0001OQ-Re for qemu-devel@nongnu.org; Thu, 04 Apr 2013 18:57:34 -0400 Received: from mail-ob0-x232.google.com ([2607:f8b0:4003:c01::232]:62544) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNt5x-0001OK-HY for qemu-devel@nongnu.org; Thu, 04 Apr 2013 18:57:25 -0400 Received: by mail-ob0-f178.google.com with SMTP id wd20so3082384obb.23 for ; Thu, 04 Apr 2013 15:57:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=O8+4Fv9Uq+OhT3gP9PV+BRgoO/pKonscfxkEQ+Lz5sE=; b=FP2RLzZ8s/B+rvLKkFUmToF5z/Krpm1Zh79xDiZ5LZey1zCoVoNaaLcOAFNIK0QXMW Mn2rq1ENYwXEDIjqSdVito3MheM4FRifsJYy6QVNQgI6pMXlYidxJjE0NJSFcyQyCatv 0Z6nxN70Ec0UfkOVCoJv7So30REbkv0gvgo+zDKKLH63LcMSH+rnN+E7D++/snV3rdZI 3VpntI+jaB5YDPez9qANw4hp+6Kh1zm/Fkx981tV0Z/YN0gHK3Ic2yGyu7CL4ku3NojC urZQUNDjAVpeOx+vvSPxlXUTSBfmZlIxSfJWXaWwyPMo0PJzQSkvRnRK+XLYDpD2c7mu PSUg== X-Received: by 10.182.27.40 with SMTP id q8mr6168303obg.100.1365116244761; Thu, 04 Apr 2013 15:57:24 -0700 (PDT) Received: from pebble.com ([12.236.175.36]) by mx.google.com with ESMTPS id j10sm9227424obg.4.2013.04.04.15.57.23 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 04 Apr 2013 15:57:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 4 Apr 2013 17:56:15 -0500 Message-Id: <1365116186-19382-23-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1365116186-19382-1-git-send-email-rth@twiddle.net> References: <1365116186-19382-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4003:c01::232 Cc: av1474@comtv.ru, Aurelien Jarno Subject: [Qemu-devel] [PATCH v4 22/33] tcg-ppc64: Handle constant inputs for some compound logicals X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Since we have special code to handle and/or/xor with a constant, apply the same to andc/orc/eqv with a constant. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 44 ++++++++++++++++++++++++++++++++++---------- 1 file changed, 34 insertions(+), 10 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 89832e5..7c326c5 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -1394,17 +1394,19 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_and_i32: + a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { - tcg_out_andi32(s, args[0], args[1], args[2]); + tcg_out_andi32(s, a0, a1, a2); } else { - tcg_out32(s, AND | SAB(args[1], args[0], args[2])); + tcg_out32(s, AND | SAB(a1, a0, a2)); } break; case INDEX_op_and_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { - tcg_out_andi64(s, args[0], args[1], args[2]); + tcg_out_andi64(s, a0, a1, a2); } else { - tcg_out32(s, AND | SAB(args[1], args[0], args[2])); + tcg_out32(s, AND | SAB(a1, a0, a2)); } break; case INDEX_op_or_i64: @@ -1426,14 +1428,36 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, } break; case INDEX_op_andc_i32: + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + tcg_out_andi32(s, a0, a1, ~a2); + } else { + tcg_out32(s, ANDC | SAB(a1, a0, a2)); + } + break; case INDEX_op_andc_i64: - tcg_out32(s, ANDC | SAB(args[1], args[0], args[2])); + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + tcg_out_andi64(s, a0, a1, ~a2); + } else { + tcg_out32(s, ANDC | SAB(a1, a0, a2)); + } break; case INDEX_op_orc_i32: + if (const_args[2]) { + tcg_out_ori32(s, args[0], args[1], ~args[2]); + break; + } + /* FALLTHRU */ case INDEX_op_orc_i64: tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); break; case INDEX_op_eqv_i32: + if (const_args[2]) { + tcg_out_xori32(s, args[0], args[1], ~args[2]); + break; + } + /* FALLTHRU */ case INDEX_op_eqv_i64: tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); break; @@ -1820,9 +1844,9 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_and_i32, { "r", "r", "ri" } }, { INDEX_op_or_i32, { "r", "r", "ri" } }, { INDEX_op_xor_i32, { "r", "r", "ri" } }, - { INDEX_op_andc_i32, { "r", "r", "r" } }, - { INDEX_op_orc_i32, { "r", "r", "r" } }, - { INDEX_op_eqv_i32, { "r", "r", "r" } }, + { INDEX_op_andc_i32, { "r", "r", "ri" } }, + { INDEX_op_orc_i32, { "r", "r", "ri" } }, + { INDEX_op_eqv_i32, { "r", "r", "ri" } }, { INDEX_op_nand_i32, { "r", "r", "r" } }, { INDEX_op_nor_i32, { "r", "r", "r" } }, @@ -1840,10 +1864,10 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_add_i64, { "r", "r", "rT" } }, { INDEX_op_sub_i64, { "r", "rI", "rT" } }, - { INDEX_op_and_i64, { "r", "r", "rU" } }, + { INDEX_op_and_i64, { "r", "r", "ri" } }, { INDEX_op_or_i64, { "r", "r", "rU" } }, { INDEX_op_xor_i64, { "r", "r", "rU" } }, - { INDEX_op_andc_i64, { "r", "r", "r" } }, + { INDEX_op_andc_i64, { "r", "r", "ri" } }, { INDEX_op_orc_i64, { "r", "r", "r" } }, { INDEX_op_eqv_i64, { "r", "r", "r" } }, { INDEX_op_nand_i64, { "r", "r", "r" } },