From patchwork Wed Mar 6 03:44:31 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 225291 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B155C2C038E for ; Wed, 6 Mar 2013 15:02:40 +1100 (EST) Received: from localhost ([::1]:45437 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UD5Ys-0007FS-T5 for incoming@patchwork.ozlabs.org; Tue, 05 Mar 2013 23:02:38 -0500 Received: from eggs.gnu.org ([208.118.235.92]:52796) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UD5Nx-0007AX-Sn for qemu-devel@nongnu.org; Tue, 05 Mar 2013 22:51:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UD5Hj-0007ww-RJ for qemu-devel@nongnu.org; Tue, 05 Mar 2013 22:45:39 -0500 Received: from ozlabs.org ([2402:b800:7003:1:1::1]:57170) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UD5Hj-0007o0-3v; Tue, 05 Mar 2013 22:44:55 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 182B02C03AC; Wed, 6 Mar 2013 14:44:44 +1100 (EST) From: David Gibson To: agraf@suse.de Date: Wed, 6 Mar 2013 14:44:31 +1100 Message-Id: <1362541473-4365-44-git-send-email-david@gibson.dropbear.id.au> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1362541473-4365-1-git-send-email-david@gibson.dropbear.id.au> References: <1362541473-4365-1-git-send-email-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2402:b800:7003:1:1::1 Cc: David Gibson , qemu-ppc@nongnu.org, afaerber@suse.de, qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH 43/45] mmu-hash*: Don't use full ppc_hash{32, 64}_translate() path for get_phys_page_debug() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Currently the hash mmu versionsof get_phys_page_debug() use the same ppc64_hash64_translate() function to do the translation logic as the normal mm fault handler code. That sounds like a good idea, but has some complications. The debug path doesn't need, or even want some parts of the full translation path, like permissions checking. Furthermore, the pte flags update included in the normal path means that the debug call is not quite side effect free. This patch, therefore, reimplements get_phys_page_debug as the minimal required subset of the full translation path. Signed-off-by: David Gibson `z --- target-ppc/mmu-hash32.c | 34 +++++++++++++++++++++++++++------- target-ppc/mmu-hash64.c | 19 ++++++++++++++++--- 2 files changed, 43 insertions(+), 10 deletions(-) diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c index 07e9b8c..5ec1a09 100644 --- a/target-ppc/mmu-hash32.c +++ b/target-ppc/mmu-hash32.c @@ -437,18 +437,38 @@ static int ppc_hash32_translate(CPUPPCState *env, struct mmu_ctx_hash32 *ctx, return 0; } -hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong addr) +hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong eaddr) { - struct mmu_ctx_hash32 ctx; + target_ulong sr; + hwaddr pte_offset; + ppc_hash_pte32_t pte; + int prot; + + if (msr_dr == 0) { + /* Translation is off */ + return eaddr; + } + + if (env->nb_BATs != 0) { + hwaddr raddr = ppc_hash32_bat_lookup(env, eaddr, 0, &prot); + if (raddr != -1) { + return raddr; + } + } + + sr = env->sr[eaddr >> 28]; + + if (sr & SR32_T) { + /* FIXME: Add suitable debug support for Direct Store segments */ + return -1; + } - /* FIXME: Will not behave sanely for direct store segments, but - * they're almost never used */ - if (unlikely(ppc_hash32_translate(env, &ctx, addr, 0) - != 0)) { + pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte); + if (pte_offset == -1) { return -1; } - return ctx.raddr & TARGET_PAGE_MASK; + return ppc_hash32_pte_raddr(sr, pte, eaddr) & TARGET_PAGE_MASK; } int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rwx, diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index d986c0f..4a7dbbb 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -449,13 +449,26 @@ static int ppc_hash64_translate(CPUPPCState *env, struct mmu_ctx_hash64 *ctx, hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr) { - struct mmu_ctx_hash64 ctx; + ppc_slb_t *slb; + hwaddr pte_offset; + ppc_hash_pte64_t pte; + + if (msr_dr == 0) { + /* In real mode the top 4 effective address bits are ignored */ + return addr & 0x0FFFFFFFFFFFFFFFULL; + } - if (unlikely(ppc_hash64_translate(env, &ctx, addr, 0) != 0)) { + slb = slb_lookup(env, addr); + if (!slb) { + return -1; + } + + pte_offset = ppc_hash64_htab_lookup(env, slb, addr, &pte); + if (pte_offset == -1) { return -1; } - return ctx.raddr & TARGET_PAGE_MASK; + return ppc_hash64_pte_raddr(slb, pte, addr) & TARGET_PAGE_MASK; } int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rwx,