From patchwork Tue Mar 5 19:00:54 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 225166 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E7A292C0315 for ; Wed, 6 Mar 2013 06:01:50 +1100 (EST) Received: from localhost ([::1]:39349 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCx7V-0003JJ-61 for incoming@patchwork.ozlabs.org; Tue, 05 Mar 2013 14:01:49 -0500 Received: from eggs.gnu.org ([208.118.235.92]:34213) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCx76-0003FP-3S for qemu-devel@nongnu.org; Tue, 05 Mar 2013 14:01:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UCx73-0005fo-Ud for qemu-devel@nongnu.org; Tue, 05 Mar 2013 14:01:24 -0500 Received: from mail-qc0-x231.google.com ([2607:f8b0:400d:c01::231]:34923) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCx73-0005fh-QW for qemu-devel@nongnu.org; Tue, 05 Mar 2013 14:01:21 -0500 Received: by mail-qc0-f177.google.com with SMTP id u28so1219709qcs.22 for ; Tue, 05 Mar 2013 11:01:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=sk3cQuKIGVwlzefFbMYecFmr+n3AdhYmXP/tp57tbWM=; b=Te7POadteu7xqa/AHeGWGNvxu+Vf8gQITTHO+EAcvFHKCNYZFsTABvifZw2r5+QZhs bdVuEIfUT/1/gVJxeQa0ga+InchXVFCa43Sdk9S6YBJdNX+eA6ChsaOxCBT3DJ3SfJW1 7VicKQOP/WTgTgjTSKd0mZv0GgfgNxoj9JnemtYI5npmevLkvLDSHlo+dx5soj6FCljv 5ljN1LSa2Co34qnB+umt0AI/XtmpWHNdhGm0AQh21AukW8r5ESBBR4DLyqc0F5ZhyV4H 5b9hIkKKSaj1eP1YAALJdEZUU0D/YCEmAs1fxgBw4pO+l+ApsFdln+KgS4+HmWLJErj6 MMeg== X-Received: by 10.49.105.100 with SMTP id gl4mr43429806qeb.23.1362510079743; Tue, 05 Mar 2013 11:01:19 -0800 (PST) Received: from yakj.usersys.redhat.com (93-34-176-20.ip50.fastwebnet.it. [93.34.176.20]) by mx.google.com with ESMTPS id q6sm3030192qeu.1.2013.03.05.11.01.17 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 05 Mar 2013 11:01:18 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 5 Mar 2013 20:00:54 +0100 Message-Id: <1362510056-3316-2-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1362510056-3316-1-git-send-email-pbonzini@redhat.com> References: <1362510056-3316-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c01::231 Cc: dwmw2@infradead.org, aliguori@us.ibm.com, lersek@redhat.com, afaerber@suse.de Subject: [Qemu-devel] [PATCH v2 1/3] cpu: make CPU_INTERRUPT_RESET available on all targets X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On the x86, some devices need access to the CPU reset pin (INIT#). Provide a generic service to do this, using one of the internal cpu_interrupt targets. Generalize the PPC-specific code for CPU_INTERRUPT_RESET to other targets, and provide a function that will raise the interrupt on all CPUs. Since PPC does not support migration, I picked the value that is used on x86, CPU_INTERRUPT_TGT_INT_1. No other arch used to use CPU_INTERRUPT_TGT_INT_1. Reviewed-by: Anthony Liguori Signed-off-by: Paolo Bonzini --- cpu-exec.c | 24 ++++++++++++++---------- cpus.c | 9 +++++++++ include/exec/cpu-all.h | 8 +++++--- include/sysemu/cpus.h | 1 + target-i386/cpu.h | 7 ++++--- target-ppc/cpu.h | 3 --- 6 files changed, 33 insertions(+), 19 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index 94fedc5..f400676 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -304,19 +304,26 @@ int cpu_exec(CPUArchState *env) } #endif #if defined(TARGET_I386) -#if !defined(CONFIG_USER_ONLY) - if (interrupt_request & CPU_INTERRUPT_POLL) { - cpu->interrupt_request &= ~CPU_INTERRUPT_POLL; - apic_poll_irq(env->apic_state); - } -#endif if (interrupt_request & CPU_INTERRUPT_INIT) { cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0); do_cpu_init(x86_env_get_cpu(env)); env->exception_index = EXCP_HALTED; cpu_loop_exit(env); - } else if (interrupt_request & CPU_INTERRUPT_SIPI) { + } +#else + if ((interrupt_request & CPU_INTERRUPT_RESET)) { + cpu_reset(cpu); + } +#endif +#if defined(TARGET_I386) +#if !defined(CONFIG_USER_ONLY) + if (interrupt_request & CPU_INTERRUPT_POLL) { + cpu->interrupt_request &= ~CPU_INTERRUPT_POLL; + apic_poll_irq(env->apic_state); + } +#endif + if (interrupt_request & CPU_INTERRUPT_SIPI) { do_cpu_sipi(x86_env_get_cpu(env)); } else if (env->hflags2 & HF2_GIF_MASK) { if ((interrupt_request & CPU_INTERRUPT_SMI) && @@ -370,9 +377,6 @@ int cpu_exec(CPUArchState *env) } } #elif defined(TARGET_PPC) - if ((interrupt_request & CPU_INTERRUPT_RESET)) { - cpu_reset(cpu); - } if (interrupt_request & CPU_INTERRUPT_HARD) { ppc_hw_interrupt(env); if (env->pending_interrupts == 0) { diff --git a/cpus.c b/cpus.c index e919dd7..87d471a 100644 --- a/cpus.c +++ b/cpus.c @@ -405,6 +405,15 @@ void hw_error(const char *fmt, ...) abort(); } +void cpu_reset_all_async(void) +{ + CPUArchState *env; + + for (env = first_cpu; env; env = env->next_cpu) { + cpu_interrupt(ENV_GET_CPU(env), CPU_INTERRUPT_RESET); + } +} + void cpu_synchronize_all_states(void) { CPUArchState *cpu; diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index e9c3717..62d2654 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -392,6 +392,9 @@ DECLARE_TLS(CPUArchState *,cpu_single_env); /* Debug event pending. */ #define CPU_INTERRUPT_DEBUG 0x0080 +/* Reset signal. */ +#define CPU_INTERRUPT_RESET 0x0400 + /* Several target-specific external hardware interrupts. Each target/cpu.h should define proper names based on these defines. */ #define CPU_INTERRUPT_TGT_EXT_0 0x0008 @@ -406,9 +409,8 @@ DECLARE_TLS(CPUArchState *,cpu_single_env); instruction being executed. These, therefore, are not masked while single-stepping within the debugger. */ #define CPU_INTERRUPT_TGT_INT_0 0x0100 -#define CPU_INTERRUPT_TGT_INT_1 0x0400 -#define CPU_INTERRUPT_TGT_INT_2 0x0800 -#define CPU_INTERRUPT_TGT_INT_3 0x2000 +#define CPU_INTERRUPT_TGT_INT_1 0x0800 +#define CPU_INTERRUPT_TGT_INT_2 0x2000 /* First unused bit: 0x4000. */ diff --git a/include/sysemu/cpus.h b/include/sysemu/cpus.h index 6502488..87b9829 100644 --- a/include/sysemu/cpus.h +++ b/include/sysemu/cpus.h @@ -7,6 +7,7 @@ void resume_all_vcpus(void); void pause_all_vcpus(void); void cpu_stop_current(void); +void cpu_reset_all_async(void); void cpu_synchronize_all_states(void); void cpu_synchronize_all_post_reset(void); void cpu_synchronize_all_post_init(void); diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 48f41ca..c7b8176 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -577,10 +577,11 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 -#define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1 -#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2 -#define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_3 +#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 +#define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 +/* CPU_INTERRUPT_RESET acts as the INIT# pin. */ +#define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET typedef enum { CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 4604a28..ceb0a12 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -2084,9 +2084,6 @@ enum { PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */ }; -/* CPU should be reset next, restart from scratch afterwards */ -#define CPU_INTERRUPT_RESET CPU_INTERRUPT_TGT_INT_0 - /*****************************************************************************/ static inline target_ulong cpu_read_xer(CPUPPCState *env)