From patchwork Mon Jan 21 03:28:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 214025 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B9E092C0040 for ; Mon, 21 Jan 2013 14:29:18 +1100 (EST) Received: from localhost ([::1]:43882 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tx84S-0006jM-TL for incoming@patchwork.ozlabs.org; Sun, 20 Jan 2013 22:29:16 -0500 Received: from eggs.gnu.org ([208.118.235.92]:35372) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tx83s-0005LI-Iz for qemu-devel@nongnu.org; Sun, 20 Jan 2013 22:28:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Tx83p-0001H6-HI for qemu-devel@nongnu.org; Sun, 20 Jan 2013 22:28:40 -0500 Received: from cantor2.suse.de ([195.135.220.15]:46161 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tx83p-0001G7-7O for qemu-devel@nongnu.org; Sun, 20 Jan 2013 22:28:37 -0500 Received: from relay1.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id ACE8BA3DDF; Mon, 21 Jan 2013 04:28:36 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Mon, 21 Jan 2013 04:28:26 +0100 Message-Id: <1358738906-13224-3-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358738906-13224-1-git-send-email-afaerber@suse.de> References: <1358738906-13224-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 195.135.220.15 Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno Subject: [Qemu-devel] [RFC qom-cpu v2 2/2] target-sh4: Move PVR/PRR/CVR into SuperHCPUClass X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org They are never changed once initialized, and moving them to the class will allow to inspect them before instantiating. Signed-off-by: Andreas Färber --- hw/sh7750.c | 10 +++++++--- target-sh4/cpu-qom.h | 6 ++++++ target-sh4/cpu.c | 18 +++++++++--------- target-sh4/cpu.h | 3 --- 4 Dateien geändert, 22 Zeilen hinzugefügt(+), 15 Zeilen entfernt(-) diff --git a/hw/sh7750.c b/hw/sh7750.c index 666f865..2259b59 100644 --- a/hw/sh7750.c +++ b/hw/sh7750.c @@ -255,6 +255,7 @@ static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr) static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr) { SH7750State *s = opaque; + SuperHCPUClass *scc; switch (addr) { case SH7750_BCR1_A7: @@ -288,11 +289,14 @@ static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr) case SH7750_CCR_A7: return s->ccr; case 0x1f000030: /* Processor version */ - return s->cpu->pvr; + scc = SUPERH_CPU_GET_CLASS(s->cpu); + return scc->pvr; case 0x1f000040: /* Cache version */ - return s->cpu->cvr; + scc = SUPERH_CPU_GET_CLASS(s->cpu); + return scc->cvr; case 0x1f000044: /* Processor revision */ - return s->cpu->prr; + scc = SUPERH_CPU_GET_CLASS(s->cpu); + return scc->prr; default: error_access("long read", addr); abort(); diff --git a/target-sh4/cpu-qom.h b/target-sh4/cpu-qom.h index 8326ceb..b264be7 100644 --- a/target-sh4/cpu-qom.h +++ b/target-sh4/cpu-qom.h @@ -40,6 +40,9 @@ * @parent_realize: The parent class' realize handler. * @parent_reset: The parent class' reset handler. * @name: The name. + * @pvr: Processor Version Register + * @prr: Processor Revision Register + * @cvr: Cache Version Register * * A SuperH CPU model. */ @@ -52,6 +55,9 @@ typedef struct SuperHCPUClass { void (*parent_reset)(CPUState *cpu); const char *name; + uint32_t pvr; + uint32_t prr; + uint32_t cvr; } SuperHCPUClass; /** diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index 80804ef..d4ba957 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -100,9 +100,6 @@ static void sh7750r_cpu_initfn(Object *obj) CPUSH4State *env = &cpu->env; env->id = SH_CPU_SH7750R; - env->pvr = 0x00050000; - env->prr = 0x00000100; - env->cvr = 0x00110000; env->features = SH_FEATURE_BCR3_AND_BCR4; } @@ -111,6 +108,9 @@ static void sh7750r_class_init(ObjectClass *oc, void *data) SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); scc->name = "SH7750R"; + scc->pvr = 0x00050000; + scc->prr = 0x00000100; + scc->cvr = 0x00110000; } static const TypeInfo sh7750r_type_info = { @@ -126,9 +126,6 @@ static void sh7751r_cpu_initfn(Object *obj) CPUSH4State *env = &cpu->env; env->id = SH_CPU_SH7751R; - env->pvr = 0x04050005; - env->prr = 0x00000113; - env->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */ env->features = SH_FEATURE_BCR3_AND_BCR4; } @@ -137,6 +134,9 @@ static void sh7751r_class_init(ObjectClass *oc, void *data) SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); scc->name = "SH7751R"; + scc->pvr = 0x04050005; + scc->prr = 0x00000113; + scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */ } static const TypeInfo sh7751r_type_info = { @@ -152,9 +152,6 @@ static void sh7785_cpu_initfn(Object *obj) CPUSH4State *env = &cpu->env; env->id = SH_CPU_SH7785; - env->pvr = 0x10300700; - env->prr = 0x00000200; - env->cvr = 0x71440211; env->features = SH_FEATURE_SH4A; } @@ -163,6 +160,9 @@ static void sh7785_class_init(ObjectClass *oc, void *data) SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); scc->name = "SH7785"; + scc->pvr = 0x10300700; + scc->prr = 0x00000200; + scc->cvr = 0x71440211; } static const TypeInfo sh7785_type_info = { diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index 49dcd9e..f805778 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -179,9 +179,6 @@ typedef struct CPUSH4State { CPU_COMMON int id; /* CPU model */ - uint32_t pvr; /* Processor Version Register */ - uint32_t prr; /* Processor Revision Register */ - uint32_t cvr; /* Cache Version Register */ void *intc_handle; int in_sleep; /* SR_BL ignored during sleep */