From patchwork Tue Jan 15 05:39:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liguang X-Patchwork-Id: 211995 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8B09E2C007B for ; Tue, 15 Jan 2013 16:42:50 +1100 (EST) Received: from localhost ([::1]:46634 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TuzIO-0006os-NV for incoming@patchwork.ozlabs.org; Tue, 15 Jan 2013 00:42:48 -0500 Received: from eggs.gnu.org ([208.118.235.92]:35583) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TuzHw-0005nX-1b for qemu-devel@nongnu.org; Tue, 15 Jan 2013 00:42:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TuzHu-0004Xx-64 for qemu-devel@nongnu.org; Tue, 15 Jan 2013 00:42:19 -0500 Received: from [222.73.24.84] (port=46783 helo=song.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TuzHt-0004XA-G5 for qemu-devel@nongnu.org; Tue, 15 Jan 2013 00:42:18 -0500 X-IronPort-AV: E=Sophos;i="4.84,471,1355068800"; d="scan'208";a="6588141" Received: from unknown (HELO tang.cn.fujitsu.com) ([10.167.250.3]) by song.cn.fujitsu.com with ESMTP; 15 Jan 2013 13:40:11 +0800 Received: from fnstmail02.fnst.cn.fujitsu.com (tang.cn.fujitsu.com [127.0.0.1]) by tang.cn.fujitsu.com (8.14.3/8.13.1) with ESMTP id r0F5gELI019165; Tue, 15 Jan 2013 13:42:15 +0800 Received: from liguang.fnst.cn.fujitsu.com ([10.167.225.128]) by fnstmail02.fnst.cn.fujitsu.com (Lotus Domino Release 8.5.3) with ESMTP id 2013011513413270-918201 ; Tue, 15 Jan 2013 13:41:32 +0800 From: liguang To: afaerber@suse.de, peter.maydell@linaro.org, imammedo@redhat.com, qemu-devel@nongnu.org Date: Tue, 15 Jan 2013 13:39:56 +0800 Message-Id: <1358228396-17552-3-git-send-email-lig.fnst@cn.fujitsu.com> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1358228396-17552-1-git-send-email-lig.fnst@cn.fujitsu.com> References: <1358228396-17552-1-git-send-email-lig.fnst@cn.fujitsu.com> X-MIMETrack: Itemize by SMTP Server on mailserver/fnst(Release 8.5.3|September 15, 2011) at 2013/01/15 13:41:32, Serialize by Router on mailserver/fnst(Release 8.5.3|September 15, 2011) at 2013/01/15 13:41:32, Serialize complete at 2013/01/15 13:41:32 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 222.73.24.84 Cc: liguang Subject: [Qemu-devel] [PATCH v5 2/2] target-i386: change some dr7 related functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org logic of some original dr7 related functions are not so readable, so try to clearify them. Signed-off-by: liguang --- target-i386/cpu.h | 13 ++++++++- target-i386/helper.c | 76 +++++++++++++++++++++++++++++++++---------------- 2 files changed, 63 insertions(+), 26 deletions(-) diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 64fd7a5..cee1cdd 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -999,9 +999,20 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, #define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault void cpu_x86_set_a20(CPUX86State *env, int a20_state); +static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index) +{ + return (dr7 >> (index * 2)) & 1; +} + +static inline bool hw_global_breakpoint_enabled(unsigned long dr7, int index) +{ + return (dr7 >> (index * 2)) & 2; + +} static inline int hw_breakpoint_enabled(unsigned long dr7, int index) { - return (dr7 >> (index * 2)) & 3; + return hw_global_breakpoint_enabled(dr7, index) || + hw_local_breakpoint_enabled(dr7, index); } static inline int hw_breakpoint_type(unsigned long dr7, int index) diff --git a/target-i386/helper.c b/target-i386/helper.c index dca1360..8d29eb5 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -966,30 +966,34 @@ hwaddr cpu_get_phys_page_debug(CPUX86State *env, target_ulong addr) void hw_breakpoint_insert(CPUX86State *env, int index) { - int type, err = 0; + int type = 0, err = 0; switch (hw_breakpoint_type(env->dr[7], index)) { - case 0: - if (hw_breakpoint_enabled(env->dr[7], index)) + case DR7_TYPE_BP_INST: + if (hw_breakpoint_enabled(env->dr[7], index)) { err = cpu_breakpoint_insert(env, env->dr[index], BP_CPU, &env->cpu_breakpoint[index]); + } break; - case 1: + case DR7_TYPE_DATA_WR: type = BP_CPU | BP_MEM_WRITE; - goto insert_wp; - case 2: - /* No support for I/O watchpoints yet */ break; - case 3: + case DR7_TYPE_DATA_RW: type = BP_CPU | BP_MEM_ACCESS; - insert_wp: + case DR7_TYPE_IO_RW: + /* No support for I/O watchpoints yet */ + break; + } + + if (type) { err = cpu_watchpoint_insert(env, env->dr[index], hw_breakpoint_len(env->dr[7], index), type, &env->cpu_watchpoint[index]); - break; } - if (err) + + if (err) { env->cpu_breakpoint[index] = NULL; + } } void hw_breakpoint_remove(CPUX86State *env, int index) @@ -997,15 +1001,16 @@ void hw_breakpoint_remove(CPUX86State *env, int index) if (!env->cpu_breakpoint[index]) return; switch (hw_breakpoint_type(env->dr[7], index)) { - case 0: - if (hw_breakpoint_enabled(env->dr[7], index)) + case DR7_TYPE_BP_INST: + if (hw_breakpoint_enabled(env->dr[7], index)) { cpu_breakpoint_remove_by_ref(env, env->cpu_breakpoint[index]); + } break; - case 1: - case 3: + case DR7_TYPE_DATA_RW: + case DR7_TYPE_DATA_WR: cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[index]); break; - case 2: + case DR7_TYPE_IO_RW: /* No support for I/O watchpoints yet */ break; } @@ -1014,22 +1019,43 @@ void hw_breakpoint_remove(CPUX86State *env, int index) int check_hw_breakpoints(CPUX86State *env, int force_dr6_update) { target_ulong dr6; - int reg, type; + int index; int hit_enabled = 0; + bool bp_match = false; + bool wp_match = false; dr6 = env->dr[6] & ~0xf; - for (reg = 0; reg < 4; reg++) { - type = hw_breakpoint_type(env->dr[7], reg); - if ((type == 0 && env->dr[reg] == env->eip) || - ((type & 1) && env->cpu_watchpoint[reg] && - (env->cpu_watchpoint[reg]->flags & BP_WATCHPOINT_HIT))) { - dr6 |= 1 << reg; - if (hw_breakpoint_enabled(env->dr[7], reg)) + for (index = 0; index < DR7_MAX_BP; index++) { + switch (hw_breakpoint_type(env->dr[7], index)) { + case DR7_TYPE_BP_INST: + if (env->dr[index] == env->eip) { + bp_match = true; + } + break; + case DR7_TYPE_DATA_WR: + case DR7_TYPE_DATA_RW: + if (env->cpu_watchpoint[index] && + env->cpu_watchpoint[index]->flags & BP_WATCHPOINT_HIT) { + wp_match = true; + } + break; + case DR7_TYPE_IO_RW: + break; + } + if (bp_match || wp_match) { + dr6 |= 1 << index; + if (hw_breakpoint_enabled(env->dr[7], index)) { hit_enabled = 1; + } + bp_match = false; + wp_match = false; } } - if (hit_enabled || force_dr6_update) + + if (hit_enabled || force_dr6_update) { env->dr[6] = dr6; + } + return hit_enabled; }