From patchwork Wed Jan 9 15:27:38 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 210727 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 592212C00EC for ; Thu, 10 Jan 2013 02:28:26 +1100 (EST) Received: from localhost ([::1]:52197 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TsxZo-0006YS-Dm for incoming@patchwork.ozlabs.org; Wed, 09 Jan 2013 10:28:24 -0500 Received: from eggs.gnu.org ([208.118.235.92]:57189) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TsxZX-0006To-Q5 for qemu-devel@nongnu.org; Wed, 09 Jan 2013 10:28:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TsxZW-0007qr-H7 for qemu-devel@nongnu.org; Wed, 09 Jan 2013 10:28:07 -0500 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:56152) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TsxZW-0007qg-AQ for qemu-devel@nongnu.org; Wed, 09 Jan 2013 10:28:06 -0500 Received: from [37.160.19.124] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TsxZR-0004ho-0T; Wed, 09 Jan 2013 16:28:05 +0100 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TsxZG-0002ww-EB; Wed, 09 Jan 2013 16:27:50 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2013 16:27:38 +0100 Message-Id: <1357745265-16084-2-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1357745265-16084-1-git-send-email-aurelien@aurel32.net> References: <1357745265-16084-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:470:1f15:c4f::1 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH v2 1/8] target-mips: fix DSP loads with rd = 0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org When rd is 0, which still need to do the actually load to possibly generate a TLB exception. Reviewed-by: Eric Johnson Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 6281e70..d1fc5af 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -12657,11 +12657,6 @@ static void gen_mipsdsp_ld(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, const char *opn = "ldx"; TCGv t0; - if (rd == 0) { - MIPS_DEBUG("NOP"); - return; - } - check_dsp(ctx); t0 = tcg_temp_new();