From patchwork Wed Dec 19 12:09:21 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 207505 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 436312C008E for ; Thu, 20 Dec 2012 05:36:37 +1100 (EST) Received: from localhost ([::1]:55409 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TlOVO-0003ca-6t for incoming@patchwork.ozlabs.org; Wed, 19 Dec 2012 13:36:34 -0500 Received: from eggs.gnu.org ([208.118.235.92]:47699) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TlOVA-0003S5-9r for qemu-devel@nongnu.org; Wed, 19 Dec 2012 13:36:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TlOV6-0007GA-Be for qemu-devel@nongnu.org; Wed, 19 Dec 2012 13:36:19 -0500 Received: from smtp02.citrix.com ([66.165.176.63]:9806) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TlOV6-0007Ee-5b for qemu-devel@nongnu.org; Wed, 19 Dec 2012 13:36:16 -0500 X-IronPort-AV: E=Sophos;i="4.84,318,1355097600"; d="scan'208";a="1241223" Received: from ftlpex01cl01.citrite.net ([10.13.107.78]) by FTLPIPO02.CITRIX.COM with ESMTP/TLS/AES128-SHA; 19 Dec 2012 18:36:13 +0000 Received: from meteora.cam.xci-test.com (10.80.248.22) by smtprelay.citrix.com (10.13.107.78) with Microsoft SMTP Server id 14.2.318.1; Wed, 19 Dec 2012 13:36:13 -0500 From: Julien Grall To: Date: Wed, 19 Dec 2012 12:09:21 +0000 Message-ID: <1355918961-3817-1-git-send-email-julien.grall@citrix.com> X-Mailer: git-send-email 1.7.10.4 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 66.165.176.63 Cc: kwolf@redhat.com, gson@gson.org, 1089996@bugs.launchpad.net, mtosatti@redhat.com, armbru@redhat.com, Julien Grall , hpoussin@reactos.org, stefanha@redhat.com, afaerber@suse.de Subject: [Qemu-devel] =?utf-8?q?=5BBug_108996_V2=5D_hw/dma=2Ec=3A_Fix_conv?= =?utf-8?q?erting_of_ioport=5Fregister*_to_MemoryRegion?= X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The commit 582299336879504353e60c7937fbc70fea93f3da introduced a 1-shift for some offset in dma emulation. Before the previous commit, which converted ioport_register_* to MemoryRegion, the DMA controller registered 8 ioports with the following formula: base + ((8 + i) << d->shift) where 0 <= i < 8 When an IO occured within a Memory Region, DMA callback receives an offset relative to the started address. Here the started address is: base + (8 << d->shift). The offset should be: (i << d->shift). After the shift is reverted, the offset are 0..7 not 1..8. Cc: 1089996@bugs.launchpad.net Reviewed-by: Andreas Färber Reported-by: Andreas Gustafsson Signed-off-by: Julien Grall Tested-by: Stefan Hajnoczi --- Modification between V1 and V2: * Modify the commit message to explain the problem. hw/dma.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/hw/dma.c b/hw/dma.c index c2d7b21..1b1d406 100644 --- a/hw/dma.c +++ b/hw/dma.c @@ -200,7 +200,7 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data, iport = (nport >> d->dshift) & 0x0f; switch (iport) { - case 0x01: /* command */ + case 0x00: /* command */ if ((data != 0) && (data & CMD_NOT_SUPPORTED)) { dolog("command %"PRIx64" not supported\n", data); return; @@ -208,7 +208,7 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data, d->command = data; break; - case 0x02: + case 0x01: ichan = data & 3; if (data & 4) { d->status |= 1 << (ichan + 4); @@ -220,7 +220,7 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data, DMA_run(); break; - case 0x03: /* single mask */ + case 0x02: /* single mask */ if (data & 4) d->mask |= 1 << (data & 3); else @@ -228,7 +228,7 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data, DMA_run(); break; - case 0x04: /* mode */ + case 0x03: /* mode */ { ichan = data & 3; #ifdef DEBUG_DMA @@ -247,23 +247,23 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data, break; } - case 0x05: /* clear flip flop */ + case 0x04: /* clear flip flop */ d->flip_flop = 0; break; - case 0x06: /* reset */ + case 0x05: /* reset */ d->flip_flop = 0; d->mask = ~0; d->status = 0; d->command = 0; break; - case 0x07: /* clear mask for all channels */ + case 0x06: /* clear mask for all channels */ d->mask = 0; DMA_run(); break; - case 0x08: /* write mask for all channels */ + case 0x07: /* write mask for all channels */ d->mask = data; DMA_run(); break; @@ -288,11 +288,11 @@ static uint64_t read_cont(void *opaque, hwaddr nport, unsigned size) iport = (nport >> d->dshift) & 0x0f; switch (iport) { - case 0x08: /* status */ + case 0x00: /* status */ val = d->status; d->status &= 0xf0; break; - case 0x0f: /* mask */ + case 0x01: /* mask */ val = d->mask; break; default: @@ -467,7 +467,7 @@ void DMA_schedule(int nchan) static void dma_reset(void *opaque) { struct dma_cont *d = opaque; - write_cont(d, (0x06 << d->dshift), 0, 1); + write_cont(d, (0x05 << d->dshift), 0, 1); } static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len)