From patchwork Fri Dec 14 02:12:01 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Scott Wood X-Patchwork-Id: 206274 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id DA65E2C009B for ; Fri, 14 Dec 2012 13:13:32 +1100 (EST) Received: from localhost ([::1]:57006 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TjKmI-0006nx-VE for incoming@patchwork.ozlabs.org; Thu, 13 Dec 2012 21:13:30 -0500 Received: from eggs.gnu.org ([208.118.235.92]:37467) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TjKlG-0004gO-Rz for qemu-devel@nongnu.org; Thu, 13 Dec 2012 21:12:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TjKlC-0005cA-Ub for qemu-devel@nongnu.org; Thu, 13 Dec 2012 21:12:26 -0500 Received: from am1ehsobe001.messaging.microsoft.com ([213.199.154.204]:34373 helo=am1outboundpool.messaging.microsoft.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TjKl4-0005Ta-FD; Thu, 13 Dec 2012 21:12:14 -0500 Received: from mail48-am1-R.bigfish.com (10.3.201.229) by AM1EHSOBE010.bigfish.com (10.3.204.30) with Microsoft SMTP Server id 14.1.225.23; Fri, 14 Dec 2012 02:12:13 +0000 Received: from mail48-am1 (localhost [127.0.0.1]) by mail48-am1-R.bigfish.com (Postfix) with ESMTP id 4319B340282; Fri, 14 Dec 2012 02:12:13 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1de0h1202h1e76h1d1ah1d2ahzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1155h) Received: from mail48-am1 (localhost.localdomain [127.0.0.1]) by mail48-am1 (MessageSwitch) id 1355451130869850_21194; Fri, 14 Dec 2012 02:12:10 +0000 (UTC) Received: from AM1EHSMHS008.bigfish.com (unknown [10.3.201.248]) by mail48-am1.bigfish.com (Postfix) with ESMTP id D220914006A; Fri, 14 Dec 2012 02:12:10 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by AM1EHSMHS008.bigfish.com (10.3.207.108) with Microsoft SMTP Server (TLS) id 14.1.225.23; Fri, 14 Dec 2012 02:12:10 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.2.318.3; Fri, 14 Dec 2012 02:12:09 +0000 Received: from snotra.am.freescale.net ([10.214.86.99]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id qBE2C4t1019223; Thu, 13 Dec 2012 19:12:07 -0700 From: Scott Wood To: Alexander Graf Date: Thu, 13 Dec 2012 20:12:01 -0600 Message-ID: <1355451124-2559-4-git-send-email-scottwood@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1355451124-2559-1-git-send-email-scottwood@freescale.com> References: <1355451124-2559-1-git-send-email-scottwood@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 X-Received-From: 213.199.154.204 Cc: Scott Wood , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH 3/6] openpic: support large vectors on FSL mpic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Previously only the spurious vector was sized appropriately to the openpic model. Also, instances of "IPVP_VECTOR(opp->spve)" were replace with just "opp->spve", as opp->spve is already just a vector and not an IVPR. Signed-off-by: Scott Wood --- hw/openpic.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/hw/openpic.c b/hw/openpic.c index 57218f3..8c3f04d 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -51,7 +51,6 @@ #define MAX_CPU 15 #define MAX_SRC 256 #define MAX_TMR 4 -#define VECTOR_BITS 8 #define MAX_IPI 4 #define MAX_MSI 8 #define MAX_IRQ (MAX_SRC + MAX_IPI + MAX_TMR) @@ -196,8 +195,7 @@ typedef struct IRQ_src_t { #define IPVP_PRIORITY_MASK (0xF << 16) #define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16)) -#define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1) -#define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK) +#define IPVP_VECTOR(opp, _ipvpr_) ((_ipvpr_) & (opp)->vector_mask) /* IDE[EP/CI] are only for FSL MPIC prior to v4.0 */ #define IDE_EP 0x80000000 /* external pin */ @@ -220,7 +218,7 @@ typedef struct OpenPICState { uint32_t nb_irqs; uint32_t vid; uint32_t veni; /* Vendor identification register */ - uint32_t spve_mask; + uint32_t vector_mask; uint32_t tifr_reset; uint32_t ipvp_reset; uint32_t ide_reset; @@ -436,7 +434,7 @@ static void openpic_reset(DeviceState *d) (opp->vid << FREP_VID_SHIFT); opp->pint = 0; - opp->spve = -1 & opp->spve_mask; + opp->spve = -1 & opp->vector_mask; opp->tifr = opp->tifr_reset; /* Initialise IRQ sources */ for (i = 0; i < opp->max_irq; i++) { @@ -485,7 +483,7 @@ static inline void write_IRQreg_ipvp(OpenPICState *opp, int n_IRQ, uint32_t val) /* NOTE: not fully accurate for special IRQs, but simple and sufficient */ /* ACTIVITY bit is read-only */ opp->src[n_IRQ].ipvp = (opp->src[n_IRQ].ipvp & IPVP_ACTIVITY_MASK) | - (val & (IPVP_MASK_MASK | IPVP_PRIORITY_MASK | IPVP_VECTOR_MASK)); + (val & (IPVP_MASK_MASK | IPVP_PRIORITY_MASK | opp->vector_mask)); openpic_update_irq(opp, n_IRQ); DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n", n_IRQ, val, opp->src[n_IRQ].ipvp); @@ -548,7 +546,7 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, } break; case 0x10E0: /* SPVE */ - opp->spve = val & opp->spve_mask; + opp->spve = val & opp->vector_mask; break; default: break; @@ -885,7 +883,7 @@ static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, DPRINTF("PIAC: irq=%d\n", n_IRQ); if (n_IRQ == -1) { /* No more interrupt pending */ - retval = IPVP_VECTOR(opp->spve); + retval = opp->spve; } else { src = &opp->src[n_IRQ]; if (!(src->ipvp & IPVP_ACTIVITY_MASK) || @@ -895,11 +893,11 @@ static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, * and the pending IRQ isn't allowed anymore */ src->ipvp &= ~IPVP_ACTIVITY_MASK; - retval = IPVP_VECTOR(opp->spve); + retval = opp->spve; } else { /* IRQ enter servicing state */ IRQ_setbit(&dst->servicing, n_IRQ); - retval = IPVP_VECTOR(src->ipvp); + retval = IPVP_VECTOR(opp, src->ipvp); } IRQ_resetbit(&dst->raised, n_IRQ); dst->raised.next = -1; @@ -1184,7 +1182,7 @@ static int openpic_init(SysBusDevice *dev) opp->nb_irqs = 80; opp->vid = VID_REVISION_1_2; opp->veni = VENI_GENERIC; - opp->spve_mask = 0xFFFF; + opp->vector_mask = 0xFFFF; opp->tifr_reset = 0; opp->ipvp_reset = IPVP_MASK_MASK; opp->ide_reset = 1 << 0; @@ -1200,7 +1198,7 @@ static int openpic_init(SysBusDevice *dev) opp->nb_irqs = RAVEN_MAX_EXT; opp->vid = VID_REVISION_1_3; opp->veni = VENI_GENERIC; - opp->spve_mask = 0xFF; + opp->vector_mask = 0xFF; opp->tifr_reset = 4160000; opp->ipvp_reset = IPVP_MASK_MASK | IPVP_MODE_MASK; opp->ide_reset = 0;