From patchwork Fri Dec 14 02:11:59 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Scott Wood X-Patchwork-Id: 206282 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9194D2C0082 for ; Fri, 14 Dec 2012 13:33:59 +1100 (EST) Received: from localhost ([::1]:56468 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TjKm1-0006Tg-2g for incoming@patchwork.ozlabs.org; Thu, 13 Dec 2012 21:13:13 -0500 Received: from eggs.gnu.org ([208.118.235.92]:37436) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TjKlE-0004cE-Lp for qemu-devel@nongnu.org; Thu, 13 Dec 2012 21:12:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TjKlB-0005ba-8z for qemu-devel@nongnu.org; Thu, 13 Dec 2012 21:12:24 -0500 Received: from va3ehsobe006.messaging.microsoft.com ([216.32.180.16]:7300 helo=va3outboundpool.messaging.microsoft.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TjKl1-0005Qz-81; Thu, 13 Dec 2012 21:12:11 -0500 Received: from mail214-va3-R.bigfish.com (10.7.14.253) by VA3EHSOBE004.bigfish.com (10.7.40.24) with Microsoft SMTP Server id 14.1.225.23; Fri, 14 Dec 2012 02:12:10 +0000 Received: from mail214-va3 (localhost [127.0.0.1]) by mail214-va3-R.bigfish.com (Postfix) with ESMTP id AEB0988013D; Fri, 14 Dec 2012 02:12:10 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1de0h1202h1e76h1d1ah1d2ahzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1155h) Received: from mail214-va3 (localhost.localdomain [127.0.0.1]) by mail214-va3 (MessageSwitch) id 1355451128435869_14672; Fri, 14 Dec 2012 02:12:08 +0000 (UTC) Received: from VA3EHSMHS011.bigfish.com (unknown [10.7.14.250]) by mail214-va3.bigfish.com (Postfix) with ESMTP id 682FBD40079; Fri, 14 Dec 2012 02:12:08 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS011.bigfish.com (10.7.99.21) with Microsoft SMTP Server (TLS) id 14.1.225.23; Fri, 14 Dec 2012 02:12:07 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.2.318.3; Fri, 14 Dec 2012 02:12:07 +0000 Received: from snotra.am.freescale.net ([10.214.86.99]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id qBE2C4sx019223; Thu, 13 Dec 2012 19:12:06 -0700 From: Scott Wood To: Alexander Graf Date: Thu, 13 Dec 2012 20:11:59 -0600 Message-ID: <1355451124-2559-2-git-send-email-scottwood@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1355451124-2559-1-git-send-email-scottwood@freescale.com> References: <1355451124-2559-1-git-send-email-scottwood@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 X-Received-From: 216.32.180.16 Cc: Scott Wood , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH 1/6] openpic: symbolicize some magic numbers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Deefine symbolic names for some register bits, and use some that have already been defined. Also convert some register values from hex to decimal when it improves readability. IPVP_PRIORITY_MASK is corrected from (0x1F << 16) to (0xF << 16), in conjunction with making wider use of the symbolic name. I looked at Freescale and IBM MPIC docs and at the base OpenPIC spec, and all three had priority as 4 bits rather than 5. Plus, the magic nubmer that is being replaced with symbolic values treated the field as 4 bits wide. Signed-off-by: Scott Wood --- hw/openpic.c | 54 ++++++++++++++++++++++++++++++++---------------------- 1 file changed, 32 insertions(+), 22 deletions(-) diff --git a/hw/openpic.c b/hw/openpic.c index 25d5cd7..7e72c29 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -124,6 +124,11 @@ #define VENI_GENERIC 0x00000000 /* Generic Vendor ID */ +#define GLBC_RESET 0x80000000 + +#define TIBC_CI 0x80000000 /* count inhibit */ +#define TICC_TOG 0x80000000 /* toggles when decrement to zero */ + #define IDR_EP_SHIFT 31 #define IDR_EP_MASK (1 << IDR_EP_SHIFT) #define IDR_CI0_SHIFT 30 @@ -189,11 +194,15 @@ typedef struct IRQ_src_t { #define IPVP_SENSE_SHIFT 22 #define IPVP_SENSE_MASK (1 << IPVP_SENSE_SHIFT) -#define IPVP_PRIORITY_MASK (0x1F << 16) +#define IPVP_PRIORITY_MASK (0xF << 16) #define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16)) #define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1) #define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK) +/* IDE[EP/CI] are only for FSL MPIC prior to v4.0 */ +#define IDE_EP 0x80000000 /* external pin */ +#define IDE_CI 0x40000000 /* critical interrupt */ + typedef struct IRQ_dst_t { uint32_t pctp; /* CPU current task priority */ uint32_t pcsr; /* CPU sensitivity register */ @@ -364,7 +373,7 @@ static void openpic_update_irq(OpenPICState *opp, int n_IRQ) DPRINTF("%s: IRQ %d is already active\n", __func__, n_IRQ); return; } - if (src->ide == 0x00000000) { + if (src->ide == 0) { /* No target */ DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ); return; @@ -421,13 +430,13 @@ static void openpic_reset(DeviceState *d) OpenPICState *opp = FROM_SYSBUS(typeof (*opp), sysbus_from_qdev(d)); int i; - opp->glbc = 0x80000000; + opp->glbc = GLBC_RESET; /* Initialise controller registers */ opp->frep = ((opp->nb_irqs -1) << FREP_NIRQ_SHIFT) | ((opp->nb_cpus -1) << FREP_NCPU_SHIFT) | (opp->vid << FREP_VID_SHIFT); - opp->pint = 0x00000000; + opp->pint = 0; opp->spve = -1 & opp->spve_mask; opp->tifr = opp->tifr_reset; /* Initialise IRQ sources */ @@ -437,7 +446,7 @@ static void openpic_reset(DeviceState *d) } /* Initialise IRQ destinations */ for (i = 0; i < MAX_CPU; i++) { - opp->dst[i].pctp = 0x0000000F; + opp->dst[i].pctp = 15; opp->dst[i].pcsr = 0x00000000; memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t)); opp->dst[i].raised.next = -1; @@ -446,11 +455,11 @@ static void openpic_reset(DeviceState *d) } /* Initialise timers */ for (i = 0; i < MAX_TMR; i++) { - opp->timers[i].ticc = 0x00000000; - opp->timers[i].tibc = 0x80000000; + opp->timers[i].ticc = 0; + opp->timers[i].tibc = TIBC_CI; } /* Go out of RESET state */ - opp->glbc = 0x00000000; + opp->glbc = 0; } static inline uint32_t read_IRQreg_ide(OpenPICState *opp, int n_IRQ) @@ -467,7 +476,7 @@ static inline void write_IRQreg_ide(OpenPICState *opp, int n_IRQ, uint32_t val) { uint32_t tmp; - tmp = val & 0xC0000000; + tmp = val & (IDE_EP | IDE_CI); tmp |= val & ((1ULL << MAX_CPU) - 1); opp->src[n_IRQ].ide = tmp; DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide); @@ -477,8 +486,8 @@ static inline void write_IRQreg_ipvp(OpenPICState *opp, int n_IRQ, uint32_t val) { /* NOTE: not fully accurate for special IRQs, but simple and sufficient */ /* ACTIVITY bit is read-only */ - opp->src[n_IRQ].ipvp = (opp->src[n_IRQ].ipvp & 0x40000000) - | (val & 0x800F00FF); + opp->src[n_IRQ].ipvp = (opp->src[n_IRQ].ipvp & IPVP_ACTIVITY_MASK) | + (val & (IPVP_MASK_MASK | IPVP_PRIORITY_MASK | IPVP_VECTOR_MASK)); openpic_update_irq(opp, n_IRQ); DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n", n_IRQ, val, opp->src[n_IRQ].ipvp); @@ -510,7 +519,7 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, case 0x1000: /* FREP */ break; case 0x1020: /* GLBC */ - if (val & 0x80000000) { + if (val & GLBC_RESET) { openpic_reset(&opp->busdev.qdev); } break; @@ -623,10 +632,11 @@ static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val, case 0x00: /* TICC (GTCCR) */ break; case 0x10: /* TIBC (GTBCR) */ - if ((opp->timers[idx].ticc & 0x80000000) != 0 && - (val & 0x80000000) == 0 && - (opp->timers[idx].tibc & 0x80000000) != 0) - opp->timers[idx].ticc &= ~0x80000000; + if ((opp->timers[idx].ticc & TICC_TOG) != 0 && + (val & TIBC_CI) == 0 && + (opp->timers[idx].tibc & TIBC_CI) != 0) { + opp->timers[idx].ticc &= ~TICC_TOG; + } opp->timers[idx].tibc = val; break; case 0x20: /* TIVP (GTIVPR) */ @@ -1179,9 +1189,9 @@ static int openpic_init(SysBusDevice *dev) opp->vid = VID_REVISION_1_2; opp->veni = VENI_GENERIC; opp->spve_mask = 0xFFFF; - opp->tifr_reset = 0x00000000; - opp->ipvp_reset = 0x80000000; - opp->ide_reset = 0x00000001; + opp->tifr_reset = 0; + opp->ipvp_reset = IPVP_MASK_MASK; + opp->ide_reset = 1 << 0; opp->max_irq = FSL_MPIC_20_MAX_IRQ; opp->irq_ipi0 = FSL_MPIC_20_IPI_IRQ; opp->irq_tim0 = FSL_MPIC_20_TMR_IRQ; @@ -1195,9 +1205,9 @@ static int openpic_init(SysBusDevice *dev) opp->vid = VID_REVISION_1_3; opp->veni = VENI_GENERIC; opp->spve_mask = 0xFF; - opp->tifr_reset = 0x003F7A00; - opp->ipvp_reset = 0xA0000000; - opp->ide_reset = 0x00000000; + opp->tifr_reset = 4160000; + opp->ipvp_reset = IPVP_MASK_MASK | IPVP_MODE_MASK; + opp->ide_reset = 0; opp->max_irq = RAVEN_MAX_IRQ; opp->irq_ipi0 = RAVEN_IPI_IRQ; opp->irq_tim0 = RAVEN_TMR_IRQ;