From patchwork Thu Nov 29 17:02:56 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 202793 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 26BCB2C0080 for ; Fri, 30 Nov 2012 04:25:31 +1100 (EST) Received: from localhost ([::1]:56421 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Te7rd-00051L-86 for incoming@patchwork.ozlabs.org; Thu, 29 Nov 2012 12:25:29 -0500 Received: from eggs.gnu.org ([208.118.235.92]:45039) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Te7rE-0004YE-K7 for qemu-devel@nongnu.org; Thu, 29 Nov 2012 12:25:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Te7r8-0001Js-Mt for qemu-devel@nongnu.org; Thu, 29 Nov 2012 12:25:04 -0500 Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1d0::1]:49817 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Te7r8-0001Je-GK for qemu-devel@nongnu.org; Thu, 29 Nov 2012 12:24:58 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1Te7Vp-0002Kc-5L; Thu, 29 Nov 2012 17:02:57 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 29 Nov 2012 17:02:56 +0000 Message-Id: <1354208577-8935-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1354208577-8935-1-git-send-email-peter.maydell@linaro.org> References: <1354208577-8935-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Cc: Igor Mitsyanko , Mark Langsdorf , Evgeny Voevodin , patches@linaro.org, Marc Zyngier , Dmitry Solodkiy , Maksim Kozlov , kvmarm@lists.cs.columbia.edu Subject: [Qemu-devel] [PATCH 2/3] hw/arm_gic: Fix comparison with priority mask register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The GIC spec states that only interrupts with higher priority than the value in the GICC_PMR priority mask register are passed through to the processor. We were incorrectly allowing through interrupts with a priority equal to the specified value: correct the comparison operation to match the spec. Signed-off-by: Peter Maydell Reviewed-by: Igor Mitsyanko --- hw/arm_gic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm_gic.c b/hw/arm_gic.c index f9e423f..672d539 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -73,7 +73,7 @@ void gic_update(GICState *s) } } level = 0; - if (best_prio <= s->priority_mask[cpu]) { + if (best_prio < s->priority_mask[cpu]) { s->current_pending[cpu] = best_irq; if (best_prio < s->running_priority[cpu]) { DPRINTF("Raised pending IRQ %d\n", best_irq);