From patchwork Thu Nov 22 03:43:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Auld X-Patchwork-Id: 200929 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 014AF2C0097 for ; Thu, 22 Nov 2012 14:43:34 +1100 (EST) Received: from localhost ([::1]:53528 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TbNhM-0002OR-Fy for incoming@patchwork.ozlabs.org; Wed, 21 Nov 2012 22:43:32 -0500 Received: from eggs.gnu.org ([208.118.235.92]:35825) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TbNhC-0002NL-GL for qemu-devel@nongnu.org; Wed, 21 Nov 2012 22:43:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TbNhA-0000NP-Rn for qemu-devel@nongnu.org; Wed, 21 Nov 2012 22:43:22 -0500 Received: from mail-pa0-f45.google.com ([209.85.220.45]:40017) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TbNhA-0000NJ-HA for qemu-devel@nongnu.org; Wed, 21 Nov 2012 22:43:20 -0500 Received: by mail-pa0-f45.google.com with SMTP id bg2so2952079pad.4 for ; Wed, 21 Nov 2012 19:43:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=subject:from:reply-to:to:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; bh=WPufKG1DY7198WzwkCDOm04gs0ZerrAFyYbwvbe4IcA=; b=wIx4W3ws6NI0B+UHKX1yPYKvEA/W2jAJlXd6TzJk33CC8aJ9D3hgldrFjHEC0XwNuJ 9z3go/MOsq8sLNb1aB9UOdvaNNf9SAQRoZ9rQACrOhqeyqjFLCJKb0CSY4wOFwM5gfpg /ctp6JGupCvCevUUvofk4PQKuimHUrQT73T1jKhdZhKvhnHb/4e++z4xgflbaU4dBlxi K5EzfYkGncNgJL6dW5y1nwRaGAv09T2WEG53CmEwNI30FupuYhN6I574QMRPiSGskosT QdnH4Id5swePjqBVepBXkVd8rTZ5S4AWuThYMv86Q50sAvLyOuckCakQVcfJLBLG6u9R VQgA== Received: by 10.68.248.10 with SMTP id yi10mr605655pbc.39.1353555798630; Wed, 21 Nov 2012 19:43:18 -0800 (PST) Received: from [192.168.0.3] (c-24-20-151-104.hsd1.or.comcast.net. [24.20.151.104]) by mx.google.com with ESMTPS id kb3sm1282652pbc.27.2012.11.21.19.43.16 (version=SSLv3 cipher=OTHER); Wed, 21 Nov 2012 19:43:17 -0800 (PST) From: Will Auld To: qemu-devel , Gleb , "mtosatti@redhat.com" , "kvm@vger.kernel.org" , "donald.d.dugger@intel.com" , "jinsong.liu@intel.com" , "xiantao.zhang@intel.com" , "will.auld@intel.com" , "avi@redhat.com" Date: Wed, 21 Nov 2012 19:43:15 -0800 Message-ID: <1353555795.7236.0.camel@WillAuldHomeLinux> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 (2.28.3-24.el6) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.220.45 Subject: [Qemu-devel] [PATCH V2] Enabling IA32_TSC_ADJUST for Qemu KVM guest VMs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list Reply-To: will.auld@intel.com List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported Basic design is to emulate the MSR by allowing reads and writes to the hypervisor vcpu specific locations to store the value of the emulated MSRs. In this way the IA32_TSC_ADJUST value will be included in all reads to the TSC MSR whether through rdmsr or rdtsc. As this is a new MSR that the guest may access and modify its value needs to be migrated along with the other MRSs. The changes here are specifically for recognizing when IA32_TSC_ADJUST is enabled in CPUID and code added for migrating its value. Signed-off-by: Will Auld --- target-i386/cpu.h | 2 ++ target-i386/kvm.c | 15 +++++++++++++++ target-i386/machine.c | 21 +++++++++++++++++++++ 3 files changed, 38 insertions(+) diff --git a/target-i386/cpu.h b/target-i386/cpu.h index aabf993..13d4152 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -284,6 +284,7 @@ #define MSR_IA32_APICBASE_BSP (1<<8) #define MSR_IA32_APICBASE_ENABLE (1<<11) #define MSR_IA32_APICBASE_BASE (0xfffff<<12) +#define MSR_TSC_ADJUST 0x0000003b #define MSR_IA32_TSCDEADLINE 0x6e0 #define MSR_MTRRcap 0xfe @@ -701,6 +702,7 @@ typedef struct CPUX86State { uint64_t async_pf_en_msr; uint64_t tsc; + uint64_t tsc_adjust; uint64_t tsc_deadline; uint64_t mcg_status; diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 696b14a..e974c42 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -61,6 +61,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = { static bool has_msr_star; static bool has_msr_hsave_pa; +static bool has_msr_tsc_adjust; static bool has_msr_tsc_deadline; static bool has_msr_async_pf_en; static bool has_msr_misc_enable; @@ -641,6 +642,10 @@ static int kvm_get_supported_msrs(KVMState *s) has_msr_hsave_pa = true; continue; } + if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) { + has_msr_tsc_adjust = true; + continue; + } if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) { has_msr_tsc_deadline = true; continue; @@ -978,6 +983,10 @@ static int kvm_put_msrs(CPUX86State *env, int level) if (has_msr_hsave_pa) { kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); } + if (has_msr_tsc_adjust) { + kvm_msr_entry_set(&msrs[n++], + MSR_TSC_ADJUST, env->tsc_adjust); + } if (has_msr_tsc_deadline) { kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline); } @@ -1234,6 +1243,9 @@ static int kvm_get_msrs(CPUX86State *env) if (has_msr_hsave_pa) { msrs[n++].index = MSR_VM_HSAVE_PA; } + if (has_msr_tsc_adjust) { + msrs[n++].index = MSR_TSC_ADJUST; + } if (has_msr_tsc_deadline) { msrs[n++].index = MSR_IA32_TSCDEADLINE; } @@ -1308,6 +1320,9 @@ static int kvm_get_msrs(CPUX86State *env) case MSR_IA32_TSC: env->tsc = msrs[i].data; break; + case MSR_TSC_ADJUST: + env->tsc_adjust = msrs[i].data; + break; case MSR_IA32_TSCDEADLINE: env->tsc_deadline = msrs[i].data; break; diff --git a/target-i386/machine.c b/target-i386/machine.c index a8be058..95bda9b 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -310,6 +310,24 @@ static const VMStateDescription vmstate_fpop_ip_dp = { } }; +static bool tsc_adjust_needed(void *opaque) +{ + CPUX86State *cpu = opaque; + + return cpu->tsc_adjust != 0; +} + +static const VMStateDescription vmstate_msr_tsc_adjust = { + .name = "cpu/msr_tsc_adjust", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_UINT64(tsc_adjust, CPUX86State), + VMSTATE_END_OF_LIST() + } +}; + static bool tscdeadline_needed(void *opaque) { CPUX86State *env = opaque; @@ -457,6 +475,9 @@ static const VMStateDescription vmstate_cpu = { .vmsd = &vmstate_fpop_ip_dp, .needed = fpop_ip_dp_needed, }, { + .vmsd = &vmstate_msr_tsc_adjust, + .needed = tsc_adjust_needed, + }, { .vmsd = &vmstate_msr_tscdeadline, .needed = tscdeadline_needed, }, {