From patchwork Thu Nov 1 13:04:21 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 196225 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B566F2C0338 for ; Fri, 2 Nov 2012 01:28:07 +1100 (EST) Received: from localhost ([::1]:42422 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TTvkb-0007hM-A2 for incoming@patchwork.ozlabs.org; Thu, 01 Nov 2012 10:28:05 -0400 Received: from eggs.gnu.org ([208.118.235.92]:59430) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TTuSZ-0005G3-FB for qemu-devel@nongnu.org; Thu, 01 Nov 2012 09:05:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TTuST-0006Ww-Td for qemu-devel@nongnu.org; Thu, 01 Nov 2012 09:05:23 -0400 Received: from mail-ie0-f173.google.com ([209.85.223.173]:62691) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TTuST-00064D-A8 for qemu-devel@nongnu.org; Thu, 01 Nov 2012 09:05:17 -0400 Received: by mail-ie0-f173.google.com with SMTP id 17so3616429iea.4 for ; Thu, 01 Nov 2012 06:05:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=XUP8P7yOJyWjCgGGUbVK6a/yqHJCnSXPCT6abwSFNa0=; b=DVgZ1C1mkNUhTfczEvvOLsplhI7Oe010GtoVtC7JNBdV4gLn5FpxCgCn0Ki2Pv/b6j cxWjZDGMfckp4tJDtMHij8v7YWRuONp7wbAKXCIsPAyx9VnbXSd2XnSr+vrxHj4gEoNs 1cxYjWmXF+iSkcCmSPgWs6S6zZccYfLGUAyzS5kr8ck5QFi42WPNenRMC9eGkK0+TYyb R98dQiGT8uAfUGM2lWQy5Txn0OGeXB0HfGliHNrxPSc5//pOuUrfW+dki4zmFgHcNEno H8IPl3Lex2VW3WIK03uDQukSNbuERhx0aRXUND80U6sD7d1xdeXMd1Mk4n26K95gnzaC IA1A== Received: by 10.50.196.193 with SMTP id io1mr1110627igc.59.1351775116636; Thu, 01 Nov 2012 06:05:16 -0700 (PDT) Received: from loki.morrigu.org (cpe-72-179-62-111.austin.res.rr.com. [72.179.62.111]) by mx.google.com with ESMTPS id dq9sm5734584igc.5.2012.11.01.06.05.15 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 01 Nov 2012 06:05:16 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Thu, 1 Nov 2012 08:04:21 -0500 Message-Id: <1351775071-7644-20-git-send-email-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1351775071-7644-1-git-send-email-mdroth@linux.vnet.ibm.com> References: <1351775071-7644-1-git-send-email-mdroth@linux.vnet.ibm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.223.173 Cc: kwolf@redhat.com, peter.maydell@linaro.org, aliguori@us.ibm.com, quintela@redhat.com, blauwirbel@gmail.com, pbonzini@redhat.com Subject: [Qemu-devel] [PATCH 19/29] shpc: qidl_declare SHPCDevice X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Also add a config_size field which we will use later to track the config size for serialization and replace unnecessary uses of SHPC_SIZEOF() with Signed-off-by: Michael Roth --- hw/shpc.c | 42 ++++++++++++++++++++++++++---------------- hw/shpc.h | 17 +++++++++++------ 2 files changed, 37 insertions(+), 22 deletions(-) diff --git a/hw/shpc.c b/hw/shpc.c index 4597bbd..92af357 100644 --- a/hw/shpc.c +++ b/hw/shpc.c @@ -6,6 +6,10 @@ #include "pci.h" #include "pci_internals.h" #include "msi.h" +#include "qidl.h" + +QIDL_ENABLE() +QIDL_IMPLEMENT_PUBLIC(SHPCDevice) /* TODO: model power only and disabled slot states. */ /* TODO: handle SERR and wakeups */ @@ -193,7 +197,7 @@ void shpc_reset(PCIDevice *d) SHPCDevice *shpc = d->shpc; int nslots = shpc->nslots; int i; - memset(shpc->config, 0, SHPC_SIZEOF(d)); + memset(shpc->config, 0, shpc->config_size); pci_set_byte(shpc->config + SHPC_NSLOTS, nslots); pci_set_long(shpc->config + SHPC_SLOTS_33, nslots); pci_set_long(shpc->config + SHPC_SLOTS_66, 0); @@ -392,10 +396,10 @@ static void shpc_write(PCIDevice *d, unsigned addr, uint64_t val, int l) { SHPCDevice *shpc = d->shpc; int i; - if (addr >= SHPC_SIZEOF(d)) { + if (addr >= shpc->config_size) { return; } - l = MIN(l, SHPC_SIZEOF(d) - addr); + l = MIN(l, shpc->config_size - addr); /* TODO: code duplicated from pci.c */ for (i = 0; i < l; val >>= 8, ++i) { @@ -415,10 +419,10 @@ static void shpc_write(PCIDevice *d, unsigned addr, uint64_t val, int l) static uint64_t shpc_read(PCIDevice *d, unsigned addr, int l) { uint64_t val = 0x0; - if (addr >= SHPC_SIZEOF(d)) { + if (addr >= d->shpc->config_size) { return val; } - l = MIN(l, SHPC_SIZEOF(d) - addr); + l = MIN(l, d->shpc->config_size - addr); memcpy(&val, d->shpc->config + addr, l); return val; } @@ -571,10 +575,11 @@ int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset) return -EINVAL; } shpc->nslots = nslots; - shpc->config = g_malloc0(SHPC_SIZEOF(d)); - shpc->cmask = g_malloc0(SHPC_SIZEOF(d)); - shpc->wmask = g_malloc0(SHPC_SIZEOF(d)); - shpc->w1cmask = g_malloc0(SHPC_SIZEOF(d)); + shpc->config_size = SHPC_SIZEOF(d); + shpc->config = g_malloc0(shpc->config_size); + shpc->cmask = g_malloc0(shpc->config_size); + shpc->wmask = g_malloc0(shpc->config_size); + shpc->w1cmask = g_malloc0(shpc->config_size); shpc_reset(d); @@ -612,7 +617,7 @@ int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset) /* TODO: init cmask */ memory_region_init_io(&shpc->mmio, &shpc_mmio_ops, d, "shpc-mmio", - SHPC_SIZEOF(d)); + shpc->config_size); shpc_cap_update_dword(d); memory_region_add_subregion(bar, offset, &shpc->mmio); pci_bus_hotplug(sec_bus, shpc_device_hotplug, &d->qdev); @@ -658,19 +663,24 @@ void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) static void shpc_save(QEMUFile *f, void *pv, size_t size) { PCIDevice *d = container_of(pv, PCIDevice, shpc); - qemu_put_buffer(f, d->shpc->config, SHPC_SIZEOF(d)); + qemu_put_buffer(f, d->shpc->config, d->shpc->config_size); +} + +void shpc_post_load(PCIDevice *d) +{ + /* Make sure we don't lose notifications. An extra interrupt is harmless. */ + d->shpc->msi_requested = 0; + shpc_interrupt_update(d); } static int shpc_load(QEMUFile *f, void *pv, size_t size) { PCIDevice *d = container_of(pv, PCIDevice, shpc); - int ret = qemu_get_buffer(f, d->shpc->config, SHPC_SIZEOF(d)); - if (ret != SHPC_SIZEOF(d)) { + int ret = qemu_get_buffer(f, d->shpc->config, d->shpc->config_size); + if (ret != d->shpc->config_size) { return -EINVAL; } - /* Make sure we don't lose notifications. An extra interrupt is harmless. */ - d->shpc->msi_requested = 0; - shpc_interrupt_update(d); + shpc_post_load(d); return 0; } diff --git a/hw/shpc.h b/hw/shpc.h index 130b71d..327e4b3 100644 --- a/hw/shpc.h +++ b/hw/shpc.h @@ -4,32 +4,36 @@ #include "qemu-common.h" #include "memory.h" #include "vmstate.h" +#include "qidl.h" -struct SHPCDevice { +QIDL_DECLARE_PUBLIC(SHPCDevice) { /* Capability offset in device's config space */ int cap; /* # of hot-pluggable slots */ int nslots; + /* size of space for SHPC working register set */ + size_t config_size; + /* SHPC WRS: working register set */ - uint8_t *config; + uint8_t *config q_size(config_size); /* Used to enable checks on load. Note that writable bits are * never checked even if set in cmask. */ - uint8_t *cmask; + uint8_t q_immutable *cmask; /* Used to implement R/W bytes */ - uint8_t *wmask; + uint8_t q_immutable *wmask; /* Used to implement RW1C(Write 1 to Clear) bytes */ - uint8_t *w1cmask; + uint8_t q_immutable *w1cmask; /* MMIO for the SHPC BAR */ MemoryRegion mmio; /* Bus controlled by this SHPC */ - PCIBus *sec_bus; + PCIBus q_elsewhere *sec_bus; /* MSI already requested for this event */ int msi_requested; @@ -40,6 +44,7 @@ int shpc_bar_size(PCIDevice *dev); int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, unsigned off); void shpc_cleanup(PCIDevice *dev, MemoryRegion *bar); void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len); +void shpc_post_load(PCIDevice *d); extern VMStateInfo shpc_vmstate_info; #define SHPC_VMSTATE(_field, _type) \