| Message ID | 1351486220-26216-1-git-send-email-rth@twiddle.net |
|---|---|
| State | New |
| Headers | show |
On Mon, Oct 29, 2012 at 03:50:20PM +1100, Richard Henderson wrote: > There is some read-after-write error within the OP=2 insns which > prevents setting cpu_dst to the real output register. Until this > is found and fixed, always write to a temporary first. > > Cc: Blue Swirl <blauwirbel@gmail.com> > Cc: Aurelien Jarno <aurelien@aurel32.net> > Signed-off-by: Richard Henderson <rth@twiddle.net> > --- > target-sparc/translate.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target-sparc/translate.c b/target-sparc/translate.c > index 4321393..9e46f14 100644 > --- a/target-sparc/translate.c > +++ b/target-sparc/translate.c > @@ -2633,7 +2633,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) > case 2: /* FPU & Logical Operations */ > { > unsigned int xop = GET_FIELD(insn, 7, 12); > - TCGv cpu_dst = gen_dest_gpr(dc, rd); > + TCGv cpu_dst = get_temp_tl(dc); > TCGv cpu_tmp0; > > if (xop == 0x3a) { /* generate trap */ Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Thanks, applied. On Mon, Oct 29, 2012 at 4:50 AM, Richard Henderson <rth@twiddle.net> wrote: > There is some read-after-write error within the OP=2 insns which > prevents setting cpu_dst to the real output register. Until this > is found and fixed, always write to a temporary first. > > Cc: Blue Swirl <blauwirbel@gmail.com> > Cc: Aurelien Jarno <aurelien@aurel32.net> > Signed-off-by: Richard Henderson <rth@twiddle.net> > --- > target-sparc/translate.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target-sparc/translate.c b/target-sparc/translate.c > index 4321393..9e46f14 100644 > --- a/target-sparc/translate.c > +++ b/target-sparc/translate.c > @@ -2633,7 +2633,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) > case 2: /* FPU & Logical Operations */ > { > unsigned int xop = GET_FIELD(insn, 7, 12); > - TCGv cpu_dst = gen_dest_gpr(dc, rd); > + TCGv cpu_dst = get_temp_tl(dc); > TCGv cpu_tmp0; > > if (xop == 0x3a) { /* generate trap */ > -- > 1.7.11.7 >
diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 4321393..9e46f14 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2633,7 +2633,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) case 2: /* FPU & Logical Operations */ { unsigned int xop = GET_FIELD(insn, 7, 12); - TCGv cpu_dst = gen_dest_gpr(dc, rd); + TCGv cpu_dst = get_temp_tl(dc); TCGv cpu_tmp0; if (xop == 0x3a) { /* generate trap */
There is some read-after-write error within the OP=2 insns which prevents setting cpu_dst to the real output register. Until this is found and fixed, always write to a temporary first. Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> --- target-sparc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)