From patchwork Wed Oct 17 21:17:26 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 192144 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 50BB72C0098 for ; Thu, 18 Oct 2012 08:14:13 +1100 (EST) Received: from localhost ([::1]:55171 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TOawN-0008B0-8o for incoming@patchwork.ozlabs.org; Wed, 17 Oct 2012 17:14:11 -0400 Received: from eggs.gnu.org ([208.118.235.92]:52345) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TOawF-0008Ap-B7 for qemu-devel@nongnu.org; Wed, 17 Oct 2012 17:14:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TOawE-0005W9-37 for qemu-devel@nongnu.org; Wed, 17 Oct 2012 17:14:03 -0400 Received: from tx2ehsobe002.messaging.microsoft.com ([65.55.88.12]:17433 helo=tx2outboundpool.messaging.microsoft.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TOawD-0005Vr-SS for qemu-devel@nongnu.org; Wed, 17 Oct 2012 17:14:02 -0400 Received: from mail258-tx2-R.bigfish.com (10.9.14.251) by TX2EHSOBE012.bigfish.com (10.9.40.32) with Microsoft SMTP Server id 14.1.225.23; Wed, 17 Oct 2012 21:14:00 +0000 Received: from mail258-tx2 (localhost [127.0.0.1]) by mail258-tx2-R.bigfish.com (Postfix) with ESMTP id 01EF416C010D; Wed, 17 Oct 2012 21:14:00 +0000 (UTC) X-Forefront-Antispam-Report: CIP:163.181.249.109; KIP:(null); UIP:(null); IPV:NLI; H:ausb3twp02.amd.com; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VPS0(zzzz1202h1d1ah1d2ahzz8275bhz2dh668h839hd24he5bhf0ah107ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1155h) Received: from mail258-tx2 (localhost.localdomain [127.0.0.1]) by mail258-tx2 (MessageSwitch) id 1350508437394265_3986; Wed, 17 Oct 2012 21:13:57 +0000 (UTC) Received: from TX2EHSMHS014.bigfish.com (unknown [10.9.14.241]) by mail258-tx2.bigfish.com (Postfix) with ESMTP id 5E0A1D00046; Wed, 17 Oct 2012 21:13:57 +0000 (UTC) Received: from ausb3twp02.amd.com (163.181.249.109) by TX2EHSMHS014.bigfish.com (10.9.99.114) with Microsoft SMTP Server id 14.1.225.23; Wed, 17 Oct 2012 21:13:57 +0000 X-WSS-ID: 0MC22Z5-02-2MU-02 X-M-MSG: Received: from sausexedgep02.amd.com (sausexedgep02-ext.amd.com [163.181.249.73]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by ausb3twp02.amd.com (Axway MailGate 3.8.1) with ESMTP id 27E23C80AE; Wed, 17 Oct 2012 16:13:53 -0500 (CDT) Received: from SAUSEXDAG01.amd.com (163.181.55.1) by sausexedgep02.amd.com (163.181.36.59) with Microsoft SMTP Server (TLS) id 8.3.192.1; Wed, 17 Oct 2012 16:29:46 -0500 Received: from STOREXDAG04.amd.com (10.1.13.13) by sausexdag01.amd.com (163.181.55.1) with Microsoft SMTP Server (TLS) id 14.2.318.4; Wed, 17 Oct 2012 16:13:54 -0500 Received: from gwo.osrc.amd.com (165.204.16.204) by storexdag04.amd.com (10.1.13.13) with Microsoft SMTP Server id 14.1.323.3; Wed, 17 Oct 2012 17:13:53 -0400 Received: from tronje.osrc.amd.com (tronje.osrc.amd.com [165.204.15.48]) by gwo.osrc.amd.com (Postfix) with ESMTP id 8986B49C14F; Wed, 17 Oct 2012 22:13:52 +0100 (BST) From: Andre Przywara To: Date: Wed, 17 Oct 2012 23:17:26 +0200 Message-ID: <1350508646-32386-1-git-send-email-andre.przywara@amd.com> X-Mailer: git-send-email 1.7.12.1 MIME-Version: 1.0 X-OriginatorOrg: amd.com X-detected-operating-system: by eggs.gnu.org: Windows XP/2000 (RFC1323+, w+, tstamp-) X-Received-From: 65.55.88.12 Cc: Andre Przywara , qemu-devel@nongnu.org, anthony@codemonkey.ws Subject: [Qemu-devel] [PATCH] i386/cpu: name new CPUID bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Update QEMU's knowledge of CPUID bit names. This allows to enable/disable those new features on QEMU's command line when using KVM and prepares future feature enablement in QEMU. This adds F16C, RDRAND, LWP, TBM, TopoExt, PerfCtr_Core, PerfCtr_NB, FSGSBASE, BMI1, AVX2, BMI2, ERMS, InvPCID, RTM, RDSeed and ADX. Sources where the AMD BKDG for Family 15h/Model 10h and the Linux kernel for the leaf 7 bits. Signed-off-by: Andre Przywara --- target-i386/cpu.c | 16 ++++++++-------- target-i386/cpu.h | 21 +++++++++++++++++++++ 2 files changed, 29 insertions(+), 8 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index f3708e6..49f9561 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -59,7 +59,7 @@ static const char *ext_feature_name[] = { NULL, "pcid", "dca", "sse4.1|sse4_1", "sse4.2|sse4_2", "x2apic", "movbe", "popcnt", "tsc-deadline", "aes", "xsave", "osxsave", - "avx", NULL, NULL, "hypervisor", + "avx", "f16c", "rdrand", "hypervisor", }; /* Feature names that are already defined on feature_name[] but are set on * CPUID[8000_0001].EDX on AMD CPUs don't have their names on @@ -79,10 +79,10 @@ static const char *ext3_feature_name[] = { "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */, "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse", "3dnowprefetch", "osvw", "ibs", "xop", - "skinit", "wdt", NULL, NULL, - "fma4", NULL, "cvt16", "nodeid_msr", - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + "skinit", "wdt", NULL, "lwp", + "fma4", "tce", NULL, "nodeid_msr", + NULL, "tbm", "topoext", "perfctr_core", + "perfctr_nb", NULL, NULL, NULL, NULL, NULL, NULL, NULL, }; @@ -105,9 +105,9 @@ static const char *svm_feature_name[] = { }; static const char *cpuid_7_0_ebx_feature_name[] = { - NULL, NULL, NULL, NULL, NULL, NULL, NULL, "smep", - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, "smap", NULL, NULL, NULL, + "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep", + "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL, + NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }; diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 871c270..e496b5b 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -403,6 +403,7 @@ #define CPUID_EXT_TM2 (1 << 8) #define CPUID_EXT_SSSE3 (1 << 9) #define CPUID_EXT_CID (1 << 10) +#define CPUID_EXT_FMA (1 << 12) #define CPUID_EXT_CX16 (1 << 13) #define CPUID_EXT_XTPR (1 << 14) #define CPUID_EXT_PDCM (1 << 15) @@ -417,6 +418,8 @@ #define CPUID_EXT_XSAVE (1 << 26) #define CPUID_EXT_OSXSAVE (1 << 27) #define CPUID_EXT_AVX (1 << 28) +#define CPUID_EXT_F16C (1 << 29) +#define CPUID_EXT_RDRAND (1 << 30) #define CPUID_EXT_HYPERVISOR (1 << 31) #define CPUID_EXT2_FPU (1 << 0) @@ -472,7 +475,15 @@ #define CPUID_EXT3_IBS (1 << 10) #define CPUID_EXT3_XOP (1 << 11) #define CPUID_EXT3_SKINIT (1 << 12) +#define CPUID_EXT3_WDT (1 << 13) +#define CPUID_EXT3_LWP (1 << 15) #define CPUID_EXT3_FMA4 (1 << 16) +#define CPUID_EXT3_TCE (1 << 17) +#define CPUID_EXT3_NODEID (1 << 19) +#define CPUID_EXT3_TBM (1 << 21) +#define CPUID_EXT3_TOPOEXT (1 << 22) +#define CPUID_EXT3_PERFCORE (1 << 23) +#define CPUID_EXT3_PERFNB (1 << 24) #define CPUID_SVM_NPT (1 << 0) #define CPUID_SVM_LBRV (1 << 1) @@ -485,7 +496,17 @@ #define CPUID_SVM_PAUSEFILTER (1 << 10) #define CPUID_SVM_PFTHRESHOLD (1 << 12) +#define CPUID_7_0_EBX_FSGSBASE (1 << 0) +#define CPUID_7_0_EBX_BMI1 (1 << 3) +#define CPUID_7_0_EBX_HLE (1 << 4) +#define CPUID_7_0_EBX_AVX2 (1 << 5) #define CPUID_7_0_EBX_SMEP (1 << 7) +#define CPUID_7_0_EBX_BMI2 (1 << 8) +#define CPUID_7_0_EBX_ERMS (1 << 9) +#define CPUID_7_0_EBX_INVPCID (1 << 10) +#define CPUID_7_0_EBX_RTM (1 << 11) +#define CPUID_7_0_EBX_RDSEED (1 << 18) +#define CPUID_7_0_EBX_ADX (1 << 19) #define CPUID_7_0_EBX_SMAP (1 << 20) #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */