From patchwork Mon Oct 15 16:39:08 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jia Liu X-Patchwork-Id: 191593 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 463F82C00B5 for ; Tue, 16 Oct 2012 03:40:43 +1100 (EST) Received: from localhost ([::1]:60218 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TNnib-0007W1-Bn for incoming@patchwork.ozlabs.org; Mon, 15 Oct 2012 12:40:41 -0400 Received: from eggs.gnu.org ([208.118.235.92]:35046) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TNniJ-0007DD-C1 for qemu-devel@nongnu.org; Mon, 15 Oct 2012 12:40:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TNniC-0006Cr-Oj for qemu-devel@nongnu.org; Mon, 15 Oct 2012 12:40:23 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:65132) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TNniC-0005pr-IL for qemu-devel@nongnu.org; Mon, 15 Oct 2012 12:40:16 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp2so5035865pbb.4 for ; Mon, 15 Oct 2012 09:40:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :content-type; bh=FfHX9/2jW1Rm0eJ6cnbrIASAFRkJjDPPHZwmYaypMNc=; b=ZV3wvW/v87ruZZjb1cIIth3zAR1OFkcpza9l0oXYzJSk9WrwoZFmI9w/5DJDwCeefB FL0naEalf8QXoKjHFFGquVHNzcPsAzr/VncZTSbJV0BD8OCMsb7g1zkp9Zh/ox2uZ6Lc gbaNvigMqzGK7Oy7QkTuK4W8TwvTe9/7N7A5t9smND0VwTrAcVQ23+aBINMeMXyUr2Mc begey4ifGK/JSsiSbgYHtCLriP7vo3dk5Fb6bJHOzxuEY4+PiGwcYGqXNrpJ6DtiLCaG BWu6beC0cgUP8atbVd8ESSKKfU1knZIcrg6GNNSEME66EheCv0GgNFtM2wRk5qxwoKSg gd/A== Received: by 10.68.204.66 with SMTP id kw2mr38924477pbc.110.1350319216176; Mon, 15 Oct 2012 09:40:16 -0700 (PDT) Received: from localhost.localdomain ([123.150.196.81]) by mx.google.com with ESMTPS id ka4sm9289654pbc.61.2012.10.15.09.40.10 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 15 Oct 2012 09:40:14 -0700 (PDT) From: Jia Liu To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2012 00:39:08 +0800 Message-Id: <1350319158-7263-5-git-send-email-proljc@gmail.com> X-Mailer: git-send-email 1.7.10.2 (Apple Git-33) In-Reply-To: <1350319158-7263-1-git-send-email-proljc@gmail.com> References: <1350319158-7263-1-git-send-email-proljc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v11 04/14] target-mips: Add ASE DSP branch instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add MIPS ASE DSP Branch instructions. Signed-off-by: Jia Liu Acked-by: Aurelien Jarno --- target-mips/translate.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/target-mips/translate.c b/target-mips/translate.c index b023d6f..f1e5bb0 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -332,6 +332,14 @@ enum { OPC_DSHD = (0x05 << 6) | OPC_DBSHFL, }; +/* MIPS DSP REGIMM opcodes */ +enum { + OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM, +#if defined(TARGET_MIPS64) + OPC_BPOSGE64 = (0x1D << 16) | OPC_REGIMM, +#endif +}; + /* Coprocessor 0 (rs field) */ #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) @@ -3224,6 +3232,16 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, } btgt = ctx->pc + insn_bytes + offset; break; + case OPC_BPOSGE32: +#if defined(TARGET_MIPS64) + case OPC_BPOSGE64: + tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F); +#else + tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F); +#endif + bcond_compute = 1; + btgt = ctx->pc + insn_bytes + offset; + break; case OPC_J: case OPC_JAL: case OPC_JALX: @@ -3412,6 +3430,16 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btgt); goto likely; + case OPC_BPOSGE32: + tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32); + MIPS_DEBUG("bposge32 " TARGET_FMT_lx, btgt); + goto not_likely; +#if defined(TARGET_MIPS64) + case OPC_BPOSGE64: + tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 64); + MIPS_DEBUG("bposge64 " TARGET_FMT_lx, btgt); + goto not_likely; +#endif case OPC_BLTZALS: case OPC_BLTZAL: ctx->hflags |= (opc == OPC_BLTZALS @@ -12583,6 +12611,14 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) check_insn(env, ctx, ISA_MIPS32R2); /* Treat as NOP. */ break; + case OPC_BPOSGE32: /* MIPS DSP branch */ +#if defined(TARGET_MIPS64) + case OPC_BPOSGE64: +#endif + check_dsp(ctx); + gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2); + *is_branch = 1; + break; default: /* Invalid */ MIPS_INVAL("regimm"); generate_exception(ctx, EXCP_RI);