From patchwork Wed Oct 3 13:29:11 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eduardo Habkost X-Patchwork-Id: 188780 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 569CA2C00BE for ; Thu, 4 Oct 2012 00:18:46 +1000 (EST) Received: from localhost ([::1]:39625 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJP0m-00069X-2d for incoming@patchwork.ozlabs.org; Wed, 03 Oct 2012 09:29:16 -0400 Received: from eggs.gnu.org ([208.118.235.92]:37218) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJP06-0004KP-0R for qemu-devel@nongnu.org; Wed, 03 Oct 2012 09:28:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TJOzt-0006bz-OL for qemu-devel@nongnu.org; Wed, 03 Oct 2012 09:28:33 -0400 Received: from mx1.redhat.com ([209.132.183.28]:17167) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJOzt-0006bM-GH for qemu-devel@nongnu.org; Wed, 03 Oct 2012 09:28:21 -0400 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q93DSK5U028495 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Wed, 3 Oct 2012 09:28:20 -0400 Received: from blackpad.lan.raisama.net (vpn1-7-147.gru2.redhat.com [10.97.7.147]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id q93DSJ8A019821; Wed, 3 Oct 2012 09:28:20 -0400 Received: by blackpad.lan.raisama.net (Postfix, from userid 500) id 403AC203604; Wed, 3 Oct 2012 10:29:21 -0300 (BRT) From: Eduardo Habkost To: qemu-devel@nongnu.org Date: Wed, 3 Oct 2012 10:29:11 -0300 Message-Id: <1349270954-4657-16-git-send-email-ehabkost@redhat.com> In-Reply-To: <1349270954-4657-1-git-send-email-ehabkost@redhat.com> References: <1349270954-4657-1-git-send-email-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.132.183.28 Cc: Igor Mammedov , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Gleb Natapov , Paolo Bonzini Subject: [Qemu-devel] [RFC 15/18] pc: set fw_cfg data based on APIC ID calculation (v2) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This changes FW_CFG_MAX_CPUS and FW_CFG_NUMA to use apic_id_for_cpu(), so the NUMA table can be based on the APIC IDs, instead of CPU index (SeaBIOS knows nothing about CPU indexes, just APIC IDs). Changes v1 -> v2: - Get PC object as argument - Add more detailed comments explaining the reason for FW_CFG_MAX_CPUS not being simply 'max_cpus' Signed-off-by: Eduardo Habkost --- hw/pc.c | 41 ++++++++++++++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 7 deletions(-) diff --git a/hw/pc.c b/hw/pc.c index 4b30f38..4c9b2f6 100644 --- a/hw/pc.c +++ b/hw/pc.c @@ -599,6 +599,15 @@ int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) return index; } +/* Returns the limit to APIC ID values + * + * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). + */ +static unsigned int apic_id_limit(PC *pc) +{ + return apic_id_for_cpu(pc, max_cpus - 1) + 1; +} + static void *bochs_bios_init(PC *pc) { void *fw_cfg; @@ -606,6 +615,7 @@ static void *bochs_bios_init(PC *pc) size_t smbios_len; uint64_t *numa_fw_cfg; int i, j; + unsigned int max_apic_id = apic_id_limit(pc); register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); @@ -614,7 +624,21 @@ static void *bochs_bios_init(PC *pc) register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); - fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); + /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: + * + * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug + * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC + * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the + * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS + * may see". + * + * So, this means we must not use max_cpus, here, but the maximum possible + * APIC ID value, plus one. + * + * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is + * the APIC ID, not the "CPU index" + */ + fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_apic_id); fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, @@ -634,21 +658,24 @@ static void *bochs_bios_init(PC *pc) * of nodes, one word for each VCPU->node and one word for each node to * hold the amount of memory. */ - numa_fw_cfg = g_malloc0((1 + max_cpus + nb_numa_nodes) * 8); + numa_fw_cfg = g_malloc0((1 + max_apic_id + nb_numa_nodes) * 8); numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); - for (i = 0; i < max_cpus; i++) { + unsigned int cpu_idx; + for (cpu_idx = 0; cpu_idx < max_cpus; cpu_idx++) { + unsigned int apic_id = apic_id_for_cpu(pc, cpu_idx); + assert(apic_id < max_apic_id); for (j = 0; j < nb_numa_nodes; j++) { - if (test_bit(i, node_cpumask[j])) { - numa_fw_cfg[i + 1] = cpu_to_le64(j); + if (test_bit(cpu_idx, node_cpumask[j])) { + numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); break; } } } for (i = 0; i < nb_numa_nodes; i++) { - numa_fw_cfg[max_cpus + 1 + i] = cpu_to_le64(node_mem[i]); + numa_fw_cfg[max_apic_id + 1 + i] = cpu_to_le64(node_mem[i]); } fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, - (1 + max_cpus + nb_numa_nodes) * 8); + (1 + max_apic_id + nb_numa_nodes) * 8); return fw_cfg; }