From patchwork Wed Oct 3 11:50:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bharat Bhushan X-Patchwork-Id: 188756 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D97D52C0097 for ; Wed, 3 Oct 2012 21:57:46 +1000 (EST) Received: from localhost ([::1]:59433 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJNaD-0001W1-5v for incoming@patchwork.ozlabs.org; Wed, 03 Oct 2012 07:57:45 -0400 Received: from eggs.gnu.org ([208.118.235.92]:53035) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJNZe-0008VO-PJ for qemu-devel@nongnu.org; Wed, 03 Oct 2012 07:57:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TJNZY-0000w8-Ti for qemu-devel@nongnu.org; Wed, 03 Oct 2012 07:57:10 -0400 Received: from co1ehsobe001.messaging.microsoft.com ([216.32.180.184]:41088 helo=co1outboundpool.messaging.microsoft.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJNZV-0000oo-6j; Wed, 03 Oct 2012 07:57:01 -0400 Received: from mail60-co1-R.bigfish.com (10.243.78.247) by CO1EHSOBE002.bigfish.com (10.243.66.65) with Microsoft SMTP Server id 14.1.225.23; Wed, 3 Oct 2012 11:56:59 +0000 Received: from mail60-co1 (localhost [127.0.0.1]) by mail60-co1-R.bigfish.com (Postfix) with ESMTP id 5FEA584007E; Wed, 3 Oct 2012 11:56:59 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 1 X-BigFish: VS1(zz168aJzz1202h1d1ah1d2ah1082kzz8275bhz2dh2a8h668h839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1155h) Received: from mail60-co1 (localhost.localdomain [127.0.0.1]) by mail60-co1 (MessageSwitch) id 1349265417613124_9166; Wed, 3 Oct 2012 11:56:57 +0000 (UTC) Received: from CO1EHSMHS019.bigfish.com (unknown [10.243.78.245]) by mail60-co1.bigfish.com (Postfix) with ESMTP id 92A91700047; Wed, 3 Oct 2012 11:56:57 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO1EHSMHS019.bigfish.com (10.243.66.29) with Microsoft SMTP Server (TLS) id 14.1.225.23; Wed, 3 Oct 2012 11:56:55 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.2.309.3; Wed, 3 Oct 2012 06:56:53 -0500 Received: from freescale.com ([10.232.15.72]) by az84smr01.freescale.net (8.14.3/8.14.0) with SMTP id q93BunKb031844; Wed, 3 Oct 2012 04:56:50 -0700 Received: by freescale.com (sSMTP sendmail emulation); Wed, 03 Oct 2012 17:20:11 +0530 From: Bharat Bhushan To: , , Date: Wed, 3 Oct 2012 17:20:00 +0530 Message-ID: <1349265000-23834-3-git-send-email-Bharat.Bhushan@freescale.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1349265000-23834-1-git-send-email-Bharat.Bhushan@freescale.com> References: <1349265000-23834-1-git-send-email-Bharat.Bhushan@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-detected-operating-system: by eggs.gnu.org: Windows XP/2000 (RFC1323+, w+, tstamp-) X-Received-From: 216.32.180.184 Cc: Bharat Bhushan Subject: [Qemu-devel] [PATCH 2/2] Adding BAR0 for e500 PCI controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org PCI Root complex have TYPE-1 configuration header while PCI endpoint have type-0 configuration header. The type-1 configuration header have a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci address space to CCSR address space. This can used for 2 purposes: 1) for MSI interrupt generation 2) Allow CCSR registers access when configured as PCI endpoint, which I am not sure is a use case with QEMU-KVM guest. What I observed is that when guest read the size of BAR0 of host controller configuration header (TYPE1 header) then it always reads it as 0. When looking into the QEMU hw/ppce500_pci.c, I do not find the PCI controller device registering BAR0. I do not find any other controller also doing so may they do not use BAR0. There are two issues when BAR0 is not there (which I can think of): 1) There should be BAR0 emulated for PCI Root comaplex (TYPE1 header) and when reading the size of BAR0, it should give size as per real h/w. This patch solves this problem. 2) Do we need this BAR0 inbound address translation? When BAR0 is of non-zero size then it will be configured for PCI address space to local address(CCSR) space translation on inbound access. The primary use case is for MSI interrupt generation. The device is configured with a address offsets in PCI address space, which will be translated to MSI interrupt generation MPIC registers. Currently I do not understand the MSI interrupt generation mechanism in QEMU and also IIRC we do not use QEMU MSI interrupt mechanism on e500 guest machines. But this BAR0 will be used when using MSI on e500. I can see one more issue, There are ATMUs emulated in hw/ppce500_pci.c, but i do not see these being used for address translation. So far that works because pci address space and local address space are 1:1 mapped. BAR0 inbound translation + ATMU translation will complete the address translation of inbound traffic. Signed-off-by: Bharat Bhushan --- hw/ppc/e500.c | 1 + hw/ppce500_pci.c | 13 +++++++++++++ 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 197411d..c7ae2b6 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -518,6 +518,7 @@ void ppce500_init(PPCE500Params *params) /* PCI */ dev = qdev_create(NULL, "e500-pcihost"); + qdev_prop_set_ptr(dev, "bar0_region", ccsr); qdev_init_nofail(dev); s = sysbus_from_qdev(dev); sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]); diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c index 92b1dc0..16e4af2 100644 --- a/hw/ppce500_pci.c +++ b/hw/ppce500_pci.c @@ -87,6 +87,7 @@ struct PPCE500PCIState { /* mmio maps */ MemoryRegion container; MemoryRegion iomem; + void *bar0; }; typedef struct PPCE500PCIState PPCE500PCIState; @@ -315,6 +316,8 @@ static int e500_pcihost_initfn(SysBusDevice *dev) int i; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *address_space_io = get_system_io(); + PCIDevice *pdev; + MemoryRegion bar0; h = PCI_HOST_BRIDGE(dev); s = PPC_E500_PCI_HOST_BRIDGE(dev); @@ -342,6 +345,10 @@ static int e500_pcihost_initfn(SysBusDevice *dev) memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem); sysbus_init_mmio(dev, &s->container); + bar0 = *(MemoryRegion *)s->bar0; + pdev = pci_find_device(b, 0, 0); + pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &bar0); + return 0; } @@ -363,6 +370,11 @@ static const TypeInfo e500_host_bridge_info = { .class_init = e500_host_bridge_class_init, }; +static Property pci_host_dev_info[] = { + DEFINE_PROP_PTR("bar0_region", PPCE500PCIState, bar0), + DEFINE_PROP_END_OF_LIST(), +}; + static void e500_pcihost_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -370,6 +382,7 @@ static void e500_pcihost_class_init(ObjectClass *klass, void *data) k->init = e500_pcihost_initfn; dc->vmsd = &vmstate_ppce500_pci; + dc->props = pci_host_dev_info; } static const TypeInfo e500_pcihost_info = {