From patchwork Thu Sep 27 23:16:06 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187542 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 372BA2C00B7 for ; Fri, 28 Sep 2012 09:16:22 +1000 (EST) Received: from localhost ([::1]:45437 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THNJc-0007nY-7j for incoming@patchwork.ozlabs.org; Thu, 27 Sep 2012 19:16:20 -0400 Received: from eggs.gnu.org ([208.118.235.92]:56217) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THNJU-0007n5-ES for qemu-devel@nongnu.org; Thu, 27 Sep 2012 19:16:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1THNJS-0006t9-Pv for qemu-devel@nongnu.org; Thu, 27 Sep 2012 19:16:12 -0400 Received: from mail-pa0-f45.google.com ([209.85.220.45]:40457) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THNJS-0006t4-GT for qemu-devel@nongnu.org; Thu, 27 Sep 2012 19:16:10 -0400 Received: by padfb10 with SMTP id fb10so1756655pad.4 for ; Thu, 27 Sep 2012 16:16:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=Hqs1hh+Flzt0BqYtZxs2Qy2ceHBQ7M4QH8W07p2unQ4=; b=xwD/32rhEzkCA5TLfYnhtm3UXG+Gl8KVO5UrHpggbMRV6Vdc2yTzUcFjCGLo5Ebi1q GGIVhlVFvk5OB6MR6vqFkd+mVG3poud6r/BflmhmrXfnRgHrXfCR6m1neQMjxcI1w1bx iH6Z79W79TtX45jVi3n062lgkRiLnKTCT+m/020uNIkRNyTUzcX1jLAOVFE7yO6FIlTY X7ZG5c5Gee2BOi8I+uKw6XGw2xnLMX+aLD2tC0yCUO115GoSf+AAavf3vrhfOGuahVJa aoM56JfieAiQhpgd+Wrsp0MkjycyeCYdS0fSoQR+PJIMs9c7XtmpjQ11X4cUpH4t99ff w2fA== Received: by 10.66.73.9 with SMTP id h9mr12873639pav.76.1348787769891; Thu, 27 Sep 2012 16:16:09 -0700 (PDT) Received: from anchor.twiddle.home.com ([173.160.232.49]) by mx.google.com with ESMTPS id pa6sm4514218pbc.71.2012.09.27.16.16.08 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 27 Sep 2012 16:16:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 Sep 2012 16:16:06 -0700 Message-Id: <1348787766-24159-1-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1348785610-23418-1-git-send-email-rth@twiddle.net> References: <1348785610-23418-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.220.45 Cc: Alexander Graf Subject: [Qemu-devel] [PATCH 038/147] target-s390: Convert TEST UNDER MASK X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-s390x/cc_helper.c | 25 ++++++---------- target-s390x/insn-data.def | 8 +++++ target-s390x/translate.c | 74 +++++++--------------------------------------- 3 files changed, 27 insertions(+), 80 deletions(-) diff --git a/target-s390x/cc_helper.c b/target-s390x/cc_helper.c index 880e3b2..99c7d57 100644 --- a/target-s390x/cc_helper.c +++ b/target-s390x/cc_helper.c @@ -20,6 +20,7 @@ #include "cpu.h" #include "helper.h" +#include "host-utils.h" /* #define DEBUG_HELPER */ #ifdef DEBUG_HELPER @@ -86,13 +87,11 @@ static inline uint32_t cc_calc_ltugtu_64(CPUS390XState *env, uint64_t src, } } -static inline uint32_t cc_calc_tm_32(CPUS390XState *env, uint32_t val, - uint32_t mask) +static uint32_t cc_calc_tm_32(CPUS390XState *env, uint32_t val, uint32_t mask) { - uint16_t r = val & mask; + uint32_t r = val & mask; - HELPER_LOG("%s: val 0x%x mask 0x%x\n", __func__, val, mask); - if (r == 0 || mask == 0) { + if (r == 0) { return 0; } else if (r == mask) { return 3; @@ -101,23 +100,17 @@ static inline uint32_t cc_calc_tm_32(CPUS390XState *env, uint32_t val, } } -/* set condition code for test under mask */ -static inline uint32_t cc_calc_tm_64(CPUS390XState *env, uint64_t val, - uint32_t mask) +static uint32_t cc_calc_tm_64(CPUS390XState *env, uint64_t val, uint64_t mask) { - uint16_t r = val & mask; + uint64_t r = val & mask; - HELPER_LOG("%s: val 0x%lx mask 0x%x r 0x%x\n", __func__, val, mask, r); - if (r == 0 || mask == 0) { + if (r == 0) { return 0; } else if (r == mask) { return 3; } else { - while (!(mask & 0x8000)) { - mask <<= 1; - val <<= 1; - } - if (val & 0x8000) { + int top = clz64(mask); + if ((int64_t)(val << top) < 0) { return 2; } else { return 1; diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 921c216..f70ede9 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -336,3 +336,11 @@ C(0xb989, SLBGR, RRE, Z, r1, r2, r1, 0, subb, subb64) C(0xe399, SLB, RXY_a, Z, r1, m2_32u, new, r1_32, subb, subb32) C(0xe389, SLBG, RXY_a, Z, r1, m2_64, r1, 0, subb, subb64) + +/* TEST UNDER MASK */ + C(0x9100, TM, SI, Z, m1_8u, i2_8u, 0, 0, 0, tm32) + C(0xeb51, TMY, SIY, LD, m1_8u, i2_8u, 0, 0, 0, tm32) + D(0xa702, TMHH, RI_a, Z, r1_o, i2_16u_shl, 0, 0, 0, tm64, 48) + D(0xa703, TMHL, RI_a, Z, r1_o, i2_16u_shl, 0, 0, 0, tm64, 32) + D(0xa700, TMLH, RI_a, Z, r1_o, i2_16u_shl, 0, 0, 0, tm64, 16) + D(0xa701, TMLL, RI_a, Z, r1_o, i2_16u_shl, 0, 0, 0, tm64, 0) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 31c08ac..ec18aeb 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -1514,16 +1514,6 @@ do_mh: tcg_temp_free_i32(tmp32_1); tcg_temp_free_i32(tmp32_2); break; - case 0x51: /* TMY D1(B1),I2 [SIY] */ - tmp = get_address(s, 0, b2, d2); /* SIY -> this is the destination */ - tmp2 = tcg_const_i64((r1 << 4) | r3); - tcg_gen_qemu_ld8u(tmp, tmp, get_mem_index(s)); - /* yes, this is a 32 bit operation with 64 bit tcg registers, because - that incurs less conversions */ - cmp_64(s, tmp, tmp2, CC_OP_TM_32); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tmp2); - break; case 0x52: /* MVIY D1(B1),I2 [SIY] */ tmp = get_address(s, 0, b2, d2); /* SIY -> this is the destination */ tmp2 = tcg_const_i64((r1 << 4) | r3); @@ -1672,44 +1662,6 @@ static void disas_ed(CPUS390XState *env, DisasContext *s, int op, int r1, tcg_temp_free_i64(addr); } -static void disas_a7(CPUS390XState *env, DisasContext *s, int op, int r1, - int i2) -{ - TCGv_i64 tmp, tmp2; - - LOG_DISAS("disas_a7: op 0x%x r1 %d i2 0x%x\n", op, r1, i2); - switch (op) { - case 0x0: /* TMLH or TMH R1,I2 [RI] */ - case 0x1: /* TMLL or TML R1,I2 [RI] */ - case 0x2: /* TMHH R1,I2 [RI] */ - case 0x3: /* TMHL R1,I2 [RI] */ - tmp = load_reg(r1); - tmp2 = tcg_const_i64((uint16_t)i2); - switch (op) { - case 0x0: - tcg_gen_shri_i64(tmp, tmp, 16); - break; - case 0x1: - break; - case 0x2: - tcg_gen_shri_i64(tmp, tmp, 48); - break; - case 0x3: - tcg_gen_shri_i64(tmp, tmp, 32); - break; - } - tcg_gen_andi_i64(tmp, tmp, 0xffff); - cmp_64(s, tmp, tmp2, CC_OP_TM_64); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tmp2); - break; - default: - LOG_DISAS("illegal a7 operation 0x%x\n", op); - gen_illegal_opcode(s); - return; - } -} - static void disas_b2(CPUS390XState *env, DisasContext *s, int op, uint32_t insn) { @@ -2678,15 +2630,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s) tcg_temp_free_i64(tmp3); tcg_temp_free_i64(tmp4); break; - case 0x91: /* TM D1(B1),I2 [SI] */ - insn = ld_code4(env, s->pc); - tmp = decode_si(s, insn, &i2, &b1, &d1); - tmp2 = tcg_const_i64(i2); - tcg_gen_qemu_ld8u(tmp, tmp, get_mem_index(s)); - cmp_64(s, tmp, tmp2, CC_OP_TM_32); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tmp2); - break; case 0x92: /* MVI D1(B1),I2 [SI] */ insn = ld_code4(env, s->pc); tmp = decode_si(s, insn, &i2, &b1, &d1); @@ -2744,13 +2687,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s) tcg_temp_free_i32(tmp32_1); tcg_temp_free_i32(tmp32_2); break; - case 0xa7: - insn = ld_code4(env, s->pc); - r1 = (insn >> 20) & 0xf; - op = (insn >> 16) & 0xf; - i2 = (short)insn; - disas_a7(env, s, op, r1, i2); - break; case 0xa8: /* MVCLE R1,R3,D2(B2) [RS] */ insn = ld_code4(env, s->pc); decode_rs(s, insn, &r1, &r3, &b2, &d2); @@ -3945,6 +3881,16 @@ static void cout_subb64(DisasContext *s, DisasOps *o) gen_op_update3_cc_i64(s, CC_OP_SUBB_64, o->in1, o->in2, o->out); } +static void cout_tm32(DisasContext *s, DisasOps *o) +{ + gen_op_update2_cc_i64(s, CC_OP_TM_32, o->in1, o->in2); +} + +static void cout_tm64(DisasContext *s, DisasOps *o) +{ + gen_op_update2_cc_i64(s, CC_OP_TM_64, o->in1, o->in2); +} + /* ====================================================================== */ /* The "PREPeration" generators. These initialize the DisasOps.OUT fields with the TCG register to which we will write. Used in combination with