From patchwork Thu Sep 27 22:39:48 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187596 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 846C42C00B5 for ; Fri, 28 Sep 2012 10:07:42 +1000 (EST) Received: from localhost ([::1]:39784 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THMm6-0004tP-34 for incoming@patchwork.ozlabs.org; Thu, 27 Sep 2012 18:41:42 -0400 Received: from eggs.gnu.org ([208.118.235.92]:35941) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THMkw-0003Qg-Mz for qemu-devel@nongnu.org; Thu, 27 Sep 2012 18:40:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1THMkt-00035Z-Jj for qemu-devel@nongnu.org; Thu, 27 Sep 2012 18:40:30 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:56587) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THMkt-00034R-0x for qemu-devel@nongnu.org; Thu, 27 Sep 2012 18:40:27 -0400 Received: by pbbrp2 with SMTP id rp2so4262246pbb.4 for ; Thu, 27 Sep 2012 15:40:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=Htux9hJqEq545YoJtjTRLNKJ3ZGmzX4eUTrNAeOH3+U=; b=gV8ns1beCTwVBsFj+ipWTaCMtIY7dh+rmLGPVgz9lv77UZAGzALMb4xnVQptiK9owS obGBb+afv9FhLQgSGFIb6UJRyAv4S4Pny3po2DHGL/etpAOgqK1jDC5GB6gI3RLtniOe FOx8Ps4qSxoejD4EomOCNeyzC0b9JLYvx8Wf4fHNfoHbJy12EBzPGoy4JuFYcrmZD2dM r/PtdNfCHKzrF2Q80chg4x0v6l4PlYz8TpY3nQQGC20U+eZVtfzjZvUjeSEIZA515WS+ DUjr4RSeTP3LHzapWG20P1j4MLvnWvMn5WrRzb4OAzn7Jtx6MT+X8Nb/LQSA9MywxtyP aYTw== Received: by 10.66.75.132 with SMTP id c4mr12906477paw.2.1348785625513; Thu, 27 Sep 2012 15:40:25 -0700 (PDT) Received: from anchor.twiddle.home.com ([173.160.232.49]) by mx.google.com with ESMTPS id sj5sm4480267pbc.30.2012.09.27.15.40.24 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 27 Sep 2012 15:40:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 Sep 2012 15:39:48 -0700 Message-Id: <1348785610-23418-8-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1348785610-23418-1-git-send-email-rth@twiddle.net> References: <1348785610-23418-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Alexander Graf Subject: [Qemu-devel] [PATCH 007/147] target-s390: Use TCG registers for FPR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org At the same time, tidy other usages of tcg_gen_deposit_i64. In some cases we can "type cast" rather than extend, and in others we can allow tcg_gen_deposit_i64 itself to optimize the HOST_LONG_BITS==32 case. Signed-off-by: Richard Henderson --- target-s390x/translate.c | 68 ++++++++++++++++++++++++++++-------------------- 1 file changed, 40 insertions(+), 28 deletions(-) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 925fd5b..e01ca1c 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -97,7 +97,7 @@ void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf, } for (i = 0; i < 16; i++) { - cpu_fprintf(f, "F%02d=%016" PRIx64, i, *(uint64_t *)&env->fregs[i]); + cpu_fprintf(f, "F%02d=%016" PRIx64, i, env->fregs[i].ll); if ((i % 4) == 3) { cpu_fprintf(f, "\n"); } else { @@ -134,21 +134,22 @@ static TCGv_i64 cc_src; static TCGv_i64 cc_dst; static TCGv_i64 cc_vr; -static char cpu_reg_names[10*3 + 6*4]; +static char cpu_reg_names[32][4]; static TCGv_i64 regs[16]; +static TCGv_i64 fregs[16]; static uint8_t gen_opc_cc_op[OPC_BUF_SIZE]; void s390x_translate_init(void) { int i; - size_t cpu_reg_names_size = sizeof(cpu_reg_names); - char *p; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - psw_addr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, psw.addr), + psw_addr = tcg_global_mem_new_i64(TCG_AREG0, + offsetof(CPUS390XState, psw.addr), "psw_addr"); - psw_mask = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, psw.mask), + psw_mask = tcg_global_mem_new_i64(TCG_AREG0, + offsetof(CPUS390XState, psw.mask), "psw_mask"); cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUS390XState, cc_op), @@ -160,13 +161,18 @@ void s390x_translate_init(void) cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_vr), "cc_vr"); - p = cpu_reg_names; for (i = 0; i < 16; i++) { - snprintf(p, cpu_reg_names_size, "r%d", i); + snprintf(cpu_reg_names[i], sizeof(cpu_reg_names[0]), "r%d", i); regs[i] = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUS390XState, regs[i]), p); - p += (i < 10) ? 3 : 4; - cpu_reg_names_size -= (i < 10) ? 3 : 4; + offsetof(CPUS390XState, regs[i]), + cpu_reg_names[i]); + } + + for (i = 0; i < 16; i++) { + snprintf(cpu_reg_names[i + 16], sizeof(cpu_reg_names[0]), "f%d", i); + fregs[i] = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUS390XState, fregs[i].d), + cpu_reg_names[i + 16]); } } @@ -180,14 +186,18 @@ static inline TCGv_i64 load_reg(int reg) static inline TCGv_i64 load_freg(int reg) { TCGv_i64 r = tcg_temp_new_i64(); - tcg_gen_ld_i64(r, cpu_env, offsetof(CPUS390XState, fregs[reg].d)); + tcg_gen_mov_i64(r, fregs[reg]); return r; } static inline TCGv_i32 load_freg32(int reg) { TCGv_i32 r = tcg_temp_new_i32(); - tcg_gen_ld_i32(r, cpu_env, offsetof(CPUS390XState, fregs[reg].l.upper)); +#if HOST_LONG_BITS == 32 + tcg_gen_mov_i32(r, TCGV_HIGH(fregs[reg])); +#else + tcg_gen_shri_i64(MAKE_TCGV_I64(GET_TCGV_I32(r)), fregs[reg], 32); +#endif return r; } @@ -212,39 +222,35 @@ static inline void store_reg(int reg, TCGv_i64 v) static inline void store_freg(int reg, TCGv_i64 v) { - tcg_gen_st_i64(v, cpu_env, offsetof(CPUS390XState, fregs[reg].d)); + tcg_gen_mov_i64(fregs[reg], v); } static inline void store_reg32(int reg, TCGv_i32 v) { + /* 32 bit register writes keep the upper half */ #if HOST_LONG_BITS == 32 tcg_gen_mov_i32(TCGV_LOW(regs[reg]), v); #else - TCGv_i64 tmp = tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(tmp, v); - /* 32 bit register writes keep the upper half */ - tcg_gen_deposit_i64(regs[reg], regs[reg], tmp, 0, 32); - tcg_temp_free_i64(tmp); + tcg_gen_deposit_i64(regs[reg], regs[reg], + MAKE_TCGV_I64(GET_TCGV_I32(v)), 0, 32); #endif } static inline void store_reg32_i64(int reg, TCGv_i64 v) { /* 32 bit register writes keep the upper half */ -#if HOST_LONG_BITS == 32 - tcg_gen_mov_i32(TCGV_LOW(regs[reg]), TCGV_LOW(v)); -#else tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32); -#endif } static inline void store_reg16(int reg, TCGv_i32 v) { - TCGv_i64 tmp = tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(tmp, v); /* 16 bit register writes keep the upper bytes */ - tcg_gen_deposit_i64(regs[reg], regs[reg], tmp, 0, 16); - tcg_temp_free_i64(tmp); +#if HOST_LONG_BITS == 32 + tcg_gen_deposit_i32(TCGV_LOW(regs[reg]), TCGV_LOW(regs[reg]), v, 0, 16); +#else + tcg_gen_deposit_i64(regs[reg], regs[reg], + MAKE_TCGV_I64(GET_TCGV_I32(v)), 0, 16); +#endif } static inline void store_reg8(int reg, TCGv_i64 v) @@ -255,7 +261,13 @@ static inline void store_reg8(int reg, TCGv_i64 v) static inline void store_freg32(int reg, TCGv_i32 v) { - tcg_gen_st_i32(v, cpu_env, offsetof(CPUS390XState, fregs[reg].l.upper)); + /* 32 bit register writes keep the lower half */ +#if HOST_LONG_BITS == 32 + tcg_gen_mov_i32(TCGV_HIGH(fregs[reg]), v); +#else + tcg_gen_deposit_i64(fregs[reg], fregs[reg], + MAKE_TCGV_I64(GET_TCGV_I32(v)), 32, 32); +#endif } static inline void update_psw_addr(DisasContext *s)