| Message ID | 1348752291-6041-5-git-send-email-proljc@gmail.com |
|---|---|
| State | New |
| Headers | show |
On Thu, Sep 27, 2012 at 09:24:41PM +0800, Jia Liu wrote: > Add MIPS ASE DSP Branch instructions. > > Signed-off-by: Jia Liu <proljc@gmail.com> > --- > target-mips/translate.c | 36 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/target-mips/translate.c b/target-mips/translate.c > index 1927781..4103f24 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -332,6 +332,14 @@ enum { > OPC_DSHD = (0x05 << 6) | OPC_DBSHFL, > }; > > +/* MIPS DSP REGIMM opcodes */ > +enum { > + OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM, > +#if defined(TARGET_MIPS64) > + OPC_BPOSGE64 = (0x1D << 16) | OPC_REGIMM, > +#endif > +}; > + > /* Coprocessor 0 (rs field) */ > #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) > > @@ -3224,6 +3232,16 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, > } > btgt = ctx->pc + insn_bytes + offset; > break; > + case OPC_BPOSGE32: > +#if defined(TARGET_MIPS64) > + case OPC_BPOSGE64: > + tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F); > +#else > + tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F); > +#endif > + bcond_compute = 1; > + btgt = ctx->pc + insn_bytes + offset; > + break; > case OPC_J: > case OPC_JAL: > case OPC_JALX: > @@ -3412,6 +3430,16 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, > tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); > MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btgt); > goto likely; > + case OPC_BPOSGE32: > + tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32); > + MIPS_DEBUG("bposge32 " TARGET_FMT_lx, btgt); > + goto not_likely; > +#if defined(TARGET_MIPS64) > + case OPC_BPOSGE64: > + tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 64); > + MIPS_DEBUG("bposge64 " TARGET_FMT_lx, btgt); > + goto not_likely; > +#endif > case OPC_BLTZALS: > case OPC_BLTZAL: > ctx->hflags |= (opc == OPC_BLTZALS > @@ -12582,6 +12610,14 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) > check_insn(env, ctx, ISA_MIPS32R2); > /* Treat as NOP. */ > break; > + case OPC_BPOSGE32: /* MIPS DSP branch */ > +#if defined(TARGET_MIPS64) > + case OPC_BPOSGE64: > +#endif > + check_dsp(ctx); > + gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2); > + *is_branch = 1; > + break; > default: /* Invalid */ > MIPS_INVAL("regimm"); > generate_exception(ctx, EXCP_RI); Looks fine to me. Acked-by: Aurelien Jarno <aurelien@aurel32.net>
diff --git a/target-mips/translate.c b/target-mips/translate.c index 1927781..4103f24 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -332,6 +332,14 @@ enum { OPC_DSHD = (0x05 << 6) | OPC_DBSHFL, }; +/* MIPS DSP REGIMM opcodes */ +enum { + OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM, +#if defined(TARGET_MIPS64) + OPC_BPOSGE64 = (0x1D << 16) | OPC_REGIMM, +#endif +}; + /* Coprocessor 0 (rs field) */ #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) @@ -3224,6 +3232,16 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, } btgt = ctx->pc + insn_bytes + offset; break; + case OPC_BPOSGE32: +#if defined(TARGET_MIPS64) + case OPC_BPOSGE64: + tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F); +#else + tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F); +#endif + bcond_compute = 1; + btgt = ctx->pc + insn_bytes + offset; + break; case OPC_J: case OPC_JAL: case OPC_JALX: @@ -3412,6 +3430,16 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btgt); goto likely; + case OPC_BPOSGE32: + tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32); + MIPS_DEBUG("bposge32 " TARGET_FMT_lx, btgt); + goto not_likely; +#if defined(TARGET_MIPS64) + case OPC_BPOSGE64: + tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 64); + MIPS_DEBUG("bposge64 " TARGET_FMT_lx, btgt); + goto not_likely; +#endif case OPC_BLTZALS: case OPC_BLTZAL: ctx->hflags |= (opc == OPC_BLTZALS @@ -12582,6 +12610,14 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) check_insn(env, ctx, ISA_MIPS32R2); /* Treat as NOP. */ break; + case OPC_BPOSGE32: /* MIPS DSP branch */ +#if defined(TARGET_MIPS64) + case OPC_BPOSGE64: +#endif + check_dsp(ctx); + gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2); + *is_branch = 1; + break; default: /* Invalid */ MIPS_INVAL("regimm"); generate_exception(ctx, EXCP_RI);
Add MIPS ASE DSP Branch instructions. Signed-off-by: Jia Liu <proljc@gmail.com> --- target-mips/translate.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)