From patchwork Fri Sep 21 16:43:29 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 185832 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 395762C0085 for ; Sat, 22 Sep 2012 02:44:15 +1000 (EST) Received: from localhost ([::1]:41486 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TF6Kr-0006tI-8Q for incoming@patchwork.ozlabs.org; Fri, 21 Sep 2012 12:44:13 -0400 Received: from eggs.gnu.org ([208.118.235.92]:48770) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TF6KT-0006c8-2E for qemu-devel@nongnu.org; Fri, 21 Sep 2012 12:43:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TF6KN-00084j-Vk for qemu-devel@nongnu.org; Fri, 21 Sep 2012 12:43:48 -0400 Received: from hall.aurel32.net ([88.191.126.93]:43338) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TF6KN-00084R-P2 for qemu-devel@nongnu.org; Fri, 21 Sep 2012 12:43:43 -0400 Received: from [37.160.47.140] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TF6KM-0003iu-HW; Fri, 21 Sep 2012 18:43:42 +0200 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TF6KC-0003rA-Dg; Fri, 21 Sep 2012 18:43:32 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Fri, 21 Sep 2012 18:43:29 +0200 Message-Id: <1348245809-13482-11-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1348245809-13482-1-git-send-email-aurelien@aurel32.net> References: <1348245809-13482-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 88.191.126.93 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH 10/10] tcg/mips: implement movcond op on MIPS32R2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org movcond operation can be implemented on MIPS32 Release 2 using the MOVN, MOVZ, SLT and SLTU instructions. Signed-off-by: Aurelien Jarno --- tcg/mips/tcg-target.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++++ tcg/mips/tcg-target.h | 8 ++++++ 2 files changed, 77 insertions(+) diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index b2e1056..44210e5 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -308,6 +308,8 @@ enum { OPC_SRAV = OPC_SPECIAL | 0x07, OPC_JR = OPC_SPECIAL | 0x08, OPC_JALR = OPC_SPECIAL | 0x09, + OPC_MOVZ = OPC_SPECIAL | 0x0A, + OPC_MOVN = OPC_SPECIAL | 0x0B, OPC_MFHI = OPC_SPECIAL | 0x10, OPC_MFLO = OPC_SPECIAL | 0x12, OPC_MULT = OPC_SPECIAL | 0x18, @@ -735,6 +737,68 @@ static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGArg arg1, reloc_pc16(label_ptr, (tcg_target_long) s->code_ptr); } +static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, + TCGArg c1, TCGArg c2, TCGArg v) +{ + switch (cond) { + case TCG_COND_EQ: + if (c1 == 0) { + tcg_out_opc_reg(s, OPC_MOVZ, ret, v, c2); + } else if (c2 == 0) { + tcg_out_opc_reg(s, OPC_MOVZ, ret, v, c1); + } else { + tcg_out_opc_reg(s, OPC_XOR, TCG_REG_AT, c1, c2); + tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT); + } + break; + case TCG_COND_NE: + if (c1 == 0) { + tcg_out_opc_reg(s, OPC_MOVN, ret, v, c2); + } else if (c2 == 0) { + tcg_out_opc_reg(s, OPC_MOVN, ret, v, c1); + } else { + tcg_out_opc_reg(s, OPC_XOR, TCG_REG_AT, c1, c2); + tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT); + } + break; + case TCG_COND_LT: + tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c1, c2); + tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT); + break; + case TCG_COND_LTU: + tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c1, c2); + tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT); + break; + case TCG_COND_GE: + tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c1, c2); + tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT); + break; + case TCG_COND_GEU: + tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c1, c2); + tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT); + break; + case TCG_COND_LE: + tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c2, c1); + tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT); + break; + case TCG_COND_LEU: + tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c2, c1); + tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT); + break; + case TCG_COND_GT: + tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c2, c1); + tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT); + break; + case TCG_COND_GTU: + tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c2, c1); + tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT); + break; + default: + tcg_abort(); + break; + } +} + static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, TCGArg arg1, TCGArg arg2) { @@ -1468,6 +1532,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_brcond2(s, args[4], args[0], args[1], args[2], args[3], args[5]); break; + case INDEX_op_movcond_i32: + tcg_out_movcond(s, args[5], args[0], args[1], args[2], args[3]); + break; + case INDEX_op_setcond_i32: tcg_out_setcond(s, args[3], args[0], args[1], args[2]); break; @@ -1559,6 +1627,7 @@ static const TCGTargetOpDef mips_op_defs[] = { { INDEX_op_deposit_i32, { "r", "0", "rZ" } }, { INDEX_op_brcond_i32, { "rZ", "rZ" } }, + { INDEX_op_movcond_i32, { "r", "r", "ri", "r", "0" } }, { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } }, { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } }, diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 897a737..d147e70 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -86,7 +86,15 @@ typedef enum { #define TCG_TARGET_HAS_orc_i32 0 #define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_nand_i32 0 + +/* optional instructions only implemented on MIPS4, MIPS32 and Loongson 2 */ +#if defined(_MIPS_ARCH_MIPS4) || defined(_MIPS_ARCH_MIPS32) || \ + defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_LOONGSON2E) || \ + defined(_MIPS_ARCH_LOONGSON2F) +#define TCG_TARGET_HAS_movcond_i32 1 +#else #define TCG_TARGET_HAS_movcond_i32 0 +#endif /* optional instructions only implemented on MIPS32R2 */ #ifdef _MIPS_ARCH_MIPS32R2