From patchwork Sun Sep 9 16:04:37 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 182635 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id F3A812C0095 for ; Mon, 10 Sep 2012 02:59:19 +1000 (EST) Received: from localhost ([::1]:56543 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAk1M-0004wO-BP for incoming@patchwork.ozlabs.org; Sun, 09 Sep 2012 12:06:04 -0400 Received: from eggs.gnu.org ([208.118.235.92]:36358) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAk0o-000456-F3 for qemu-devel@nongnu.org; Sun, 09 Sep 2012 12:05:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TAk0m-00089q-ON for qemu-devel@nongnu.org; Sun, 09 Sep 2012 12:05:30 -0400 Received: from mail-lpp01m010-f45.google.com ([209.85.215.45]:63685) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAk0m-0007WX-HL for qemu-devel@nongnu.org; Sun, 09 Sep 2012 12:05:28 -0400 Received: by mail-lpp01m010-f45.google.com with SMTP id z14so574040lag.4 for ; Sun, 09 Sep 2012 09:05:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=PXE1IWkQz8Vj9lDVKYJSUXCFn/IZhvoiKGvAbEFsDm0=; b=cv4uFSCfI887CTJATSMajFwr4gHKWGckxDwqrrgZMVEYh2VryUV8J9GHV1waIbtIGj q4mmA890qstDUc/jISzxEUTxn0QUuu+O5GhRz4S0jsTZ8/uuB81EFS0QLCLWtczLre0Q tDE4fLjJN2azoTFhNA2ZQBhZAL4xMdiOhrz4edA8SL/0UNC9pAzXNOu5r/RPz3kt76zI 0wP/Rort/ASosWUVjD9OdZJe1UK8Qeth/awtcg96brcln7rP4rQpSKiA7ETx3Jd+qtfc XhdbnAEL7nPMgqghqUkHomV62uOnecIjH7yLu4FDzEcaWyOjvIIZj8XUMm4vwnspq/Su MmFA== Received: by 10.152.144.168 with SMTP id sn8mr10201049lab.1.1347206728119; Sun, 09 Sep 2012 09:05:28 -0700 (PDT) Received: from octofox.metropolis ([188.134.19.124]) by mx.google.com with ESMTPS id in6sm8995530lab.1.2012.09.09.09.05.25 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 09 Sep 2012 09:05:27 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Sun, 9 Sep 2012 20:04:37 +0400 Message-Id: <1347206679-428-9-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 1.7.7.6 In-Reply-To: <1347206679-428-1-git-send-email-jcmvbkbc@gmail.com> References: <1347206679-428-1-git-send-email-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.215.45 Cc: Blue Swirl , Peter Maydell , Max Filippov Subject: [Qemu-devel] [PATCH v2 08/10] target-xtensa: implement FP0 conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org These are FP to integer and integer to FP conversion opcodes. See ISA, 4.3.10 for more details. Note that utrunc.s implementation follows ISS behaviour, not ISA. Signed-off-by: Max Filippov --- Changes v1->v2: - replace float32_mul/div in FP-to-integer convertors with float32_scalbn - reimplement comparison with zero in FP-to-integer convertors target-xtensa/helper.h | 4 +++ target-xtensa/op_helper.c | 37 ++++++++++++++++++++++++++++++++++ target-xtensa/translate.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 89 insertions(+), 0 deletions(-) diff --git a/target-xtensa/helper.h b/target-xtensa/helper.h index 4e6e417..9557347 100644 --- a/target-xtensa/helper.h +++ b/target-xtensa/helper.h @@ -44,5 +44,9 @@ DEF_HELPER_3(sub_s, f32, env, f32, f32) DEF_HELPER_3(mul_s, f32, env, f32, f32) DEF_HELPER_4(madd_s, f32, env, f32, f32, f32) DEF_HELPER_4(msub_s, f32, env, f32, f32, f32) +DEF_HELPER_FLAGS_3(ftoi, TCG_CALL_CONST | TCG_CALL_PURE, i32, f32, i32, i32) +DEF_HELPER_FLAGS_3(ftoui, TCG_CALL_CONST | TCG_CALL_PURE, i32, f32, i32, i32) +DEF_HELPER_3(itof, f32, env, i32, i32) +DEF_HELPER_3(uitof, f32, env, i32, i32) #include "def-helper.h" diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index ba935a8..5cf9c02 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -821,3 +821,40 @@ float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c) return float32_muladd(b, c, a, float_muladd_negate_product, &env->fp_status); } + +uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale) +{ + float_status fp_status = {0}; + + set_float_rounding_mode(rounding_mode, &fp_status); + return float32_to_int32( + float32_scalbn(v, scale, &fp_status), &fp_status); +} + +uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale) +{ + float_status fp_status = {0}; + float32 res; + + set_float_rounding_mode(rounding_mode, &fp_status); + + res = float32_scalbn(v, scale, &fp_status); + + if (float32_is_neg(v) && !float32_is_any_nan(v)) { + return float32_to_int32(res, &fp_status); + } else { + return float32_to_uint32(res, &fp_status); + } +} + +float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale) +{ + return float32_scalbn(int32_to_float32(v, &env->fp_status), + (int32_t)scale, &env->fp_status); +} + +float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale) +{ + return float32_scalbn(uint32_to_float32(v, &env->fp_status), + (int32_t)scale, &env->fp_status); +} diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index a2ce286..fabde4f 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -1915,6 +1915,54 @@ static void disas_xtensa_insn(DisasContext *dc) cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]); break; + case 8: /*ROUND.Sf*/ + case 9: /*TRUNC.Sf*/ + case 10: /*FLOOR.Sf*/ + case 11: /*CEIL.Sf*/ + case 14: /*UTRUNC.Sf*/ + gen_window_check1(dc, RRR_R); + { + static const unsigned rounding_mode_const[] = { + float_round_nearest_even, + float_round_to_zero, + float_round_down, + float_round_up, + [6] = float_round_to_zero, + }; + TCGv_i32 rounding_mode = tcg_const_i32( + rounding_mode_const[OP2 & 7]); + TCGv_i32 scale = tcg_const_i32(RRR_T); + + if (OP2 == 14) { + gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S], + rounding_mode, scale); + } else { + gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S], + rounding_mode, scale); + } + + tcg_temp_free(rounding_mode); + tcg_temp_free(scale); + } + break; + + case 12: /*FLOAT.Sf*/ + case 13: /*UFLOAT.Sf*/ + gen_window_check1(dc, RRR_S); + { + TCGv_i32 scale = tcg_const_i32(-RRR_T); + + if (OP2 == 13) { + gen_helper_uitof(cpu_FR[RRR_R], cpu_env, + cpu_R[RRR_S], scale); + } else { + gen_helper_itof(cpu_FR[RRR_R], cpu_env, + cpu_R[RRR_S], scale); + } + tcg_temp_free(scale); + } + break; + case 15: /*FP1OP*/ switch (RRR_T) { case 0: /*MOV.Sf*/