From patchwork Wed Jul 25 17:06:12 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Catalin Patulea X-Patchwork-Id: 173221 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8A3AB2C009B for ; Thu, 26 Jul 2012 03:07:21 +1000 (EST) Received: from localhost ([::1]:34985 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Su53P-0000LH-JH for incoming@patchwork.ozlabs.org; Wed, 25 Jul 2012 13:07:19 -0400 Received: from eggs.gnu.org ([208.118.235.92]:56091) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Su53H-0000Kk-0V for qemu-devel@nongnu.org; Wed, 25 Jul 2012 13:07:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Su53E-0005BM-PT for qemu-devel@nongnu.org; Wed, 25 Jul 2012 13:07:10 -0400 Received: from mail-gg0-f173.google.com ([209.85.161.173]:51459) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Su53E-0005Ax-Iv for qemu-devel@nongnu.org; Wed, 25 Jul 2012 13:07:08 -0400 Received: by ggnp1 with SMTP id p1so936340ggn.4 for ; Wed, 25 Jul 2012 10:07:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=cOpchpbAdGf1VU23ihCQSUe+b8VHYR1/cpcBHNQDyBM=; b=hazPvrDRkA9Ni72eDXPACbIScv9WFftE9dG5MX+rbd+yp72sQpkz+GfpjMLY9EZFzJ MHbxgLVQNWdEw5hzwcHUDKLNeAB50BlVOxRpBI8BJtKmqNL2ip7lWTs9T2+H0fC8H2zd jW8CYZyFEhZ1wx9vC2n2Hn1ooKuW4CsPCYwbFpqe5FcZTxuk7yW3WYp4jrS0GovVOY1d 1K0Z0Xfvdiz9p0R9CYQg3ZNPC2B6crs+pFrOSNOdhimi8bvOiWbEZP/GWjXSgxJ4F8cC o8hRBa1o/sWN0NxQXT+1KOQvFLrAfffbMooFW65qqw6MpCrisHXTej/UVAFVip2Fqwax DCFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=cOpchpbAdGf1VU23ihCQSUe+b8VHYR1/cpcBHNQDyBM=; b=e+EP1DOrBAcR2hqMDqUEarujdrJgWV09o/xi5ptxCJYymi0HWkXnijjS/n/B6Dh8fM TI1TncxNolVFyR9oGX9vxMx4CQEkL4hPknn62GCL76EKB4mjYOLXSEkWFG57dZ+NzDjG pAW3Gt+JxrWvGKDC8oEbmmPvJ/UswzqpDFTEndJ5cvxdA4YIqCbMGVbdkWxHkIfe5aDi pgLE1wngksqrIl+GizhblFxgnrq/nSIGzvYOkHJqwISd/vsev5EL3YdPITZUTvXoN26c D8T3puiGBEtnMJKfu0JVeUyJHpsHSb3v/jJ3fcA38eaEOI35Gxr2a3foJwG9Tvtx/1Zo 5pPw== Received: by 10.43.104.202 with SMTP id dn10mr25961896icc.29.1343236027575; Wed, 25 Jul 2012 10:07:07 -0700 (PDT) Received: by 10.43.104.202 with SMTP id dn10mr25961876icc.29.1343236027431; Wed, 25 Jul 2012 10:07:07 -0700 (PDT) Received: from gibson.mon.corp.google.com (gibson.mon.corp.google.com [172.29.33.50]) by mx.google.com with ESMTPS id qo3sm3327251igc.8.2012.07.25.10.07.05 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 25 Jul 2012 10:07:06 -0700 (PDT) From: Catalin Patulea To: qemu-devel@nongnu.org Date: Wed, 25 Jul 2012 13:06:12 -0400 Message-Id: <1343235972-8916-1-git-send-email-catalinp@google.com> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: References: X-Gm-Message-State: ALoCoQkk4/+84A/hTu1lv/mC9bU098Ko20ptz3Pm3Prkw1DkoBEmD8O4ZiiaHjEB5hEfXuIEM8TErvvT4HP5PdWdaQs1JV1c9vuh6vKVwtrmTdotx3OwWHIGWDOoqCjZ+S4APYPc1ShFgYMT/4eaOFhep3jlIJVowm9gwA02fuEnjlMGmNidS3KAt2lYWOhEfr5I+udWHR21FI743sjv0Zs5H48Oj9wczQ== X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.161.173 Cc: Peter Maydell , Catalin Patulea Subject: [Qemu-devel] [PATCH v2] tests/tcg: add test-i386-fprem and make target for comparing QEMU to h/w X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This test contains manual and automatically-generated test cases, in the style of test-i386 (run on h/w, run on QEMU, diff the outputs), for the FPREM instruction. For each test case, the input operands, result and FPU status word are printed. The manual cases are inspired from the instruction spec and get basic coverage of all exceptions FPREM can generate. They also test some "special" exceptions like stack underflow (when the FPU stack contains only one operand). The automated cases are generated from all pairs of extreme values in the bitfields that make up the input operands. This gives rise to a range of numeric values, NaNs, infinities, and other special values. FPREM raises either no exceptions, invalid or denormal, and these cases are intended to get good code path coverage of the implementation. Signed-off-by: Catalin Patulea --- tests/tcg/Makefile | 9 ++ tests/tcg/test-i386-fprem.c | 325 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 334 insertions(+), 0 deletions(-) create mode 100644 tests/tcg/test-i386-fprem.c diff --git a/tests/tcg/Makefile b/tests/tcg/Makefile index 9ff47b8..06cd563 100644 --- a/tests/tcg/Makefile +++ b/tests/tcg/Makefile @@ -22,6 +22,7 @@ I386_TESTS=hello-i386 \ testthread \ sha1-i386 \ test-i386 \ + test-i386-fprem \ test-mmap \ # runcom @@ -55,6 +56,11 @@ run-test-i386: test-i386 -$(QEMU) test-i386 > test-i386.out @if diff -u test-i386.ref test-i386.out ; then echo "Auto Test OK"; fi +run-test-i386-fprem: test-i386-fprem + ./test-i386-fprem > test-i386-fprem.ref + -$(QEMU) test-i386-fprem > test-i386-fprem.out + @if diff -u test-i386-fprem.ref test-i386-fprem.out ; then echo "Auto Test OK"; fi + run-test-x86_64: test-x86_64 ./test-x86_64 > test-x86_64.ref -$(QEMU_X86_64) test-x86_64 > test-x86_64.out @@ -93,6 +99,9 @@ test-i386: test-i386.c test-i386-code16.S test-i386-vm86.S \ $(CC_I386) $(QEMU_INCLUDES) $(CFLAGS) $(LDFLAGS) -o $@ \ $(. + */ +#include "compiler.h" +#include "osdep.h" +#include +#include + +/* + * Inspired by 's union ieee854_long_double, but with single + * long long mantissa fields and assuming little-endianness for simplicity. + */ +union float80u { + long double d; + + /* This is the IEEE 854 double-extended-precision format. */ + struct { + unsigned long long mantissa:63; + unsigned int one:1; + unsigned int exponent:15; + unsigned int negative:1; + unsigned int empty:16; + } QEMU_PACKED ieee; + + /* This is for NaNs in the IEEE 854 double-extended-precision format. */ + struct { + unsigned long long mantissa:62; + unsigned int quiet_nan:1; + unsigned int one:1; + unsigned int exponent:15; + unsigned int negative:1; + unsigned int empty:16; + } QEMU_PACKED ieee_nan; +}; + +#define IEEE854_LONG_DOUBLE_BIAS 0x3fff + +static const union float80u q_nan = { + .ieee_nan.negative = 0, /* X */ + .ieee_nan.exponent = 0x7fff, + .ieee_nan.one = 1, + .ieee_nan.quiet_nan = 1, + .ieee_nan.mantissa = 0, +}; + +static const union float80u s_nan = { + .ieee_nan.negative = 0, /* X */ + .ieee_nan.exponent = 0x7fff, + .ieee_nan.one = 1, + .ieee_nan.quiet_nan = 0, + .ieee_nan.mantissa = 1, /* nonzero */ +}; + +static const union float80u pos_inf = { + .ieee.negative = 0, + .ieee.exponent = 0x7fff, + .ieee.one = 1, + .ieee.mantissa = 0, +}; + +static const union float80u pseudo_pos_inf = { /* "unsupported" */ + .ieee.negative = 0, + .ieee.exponent = 0x7fff, + .ieee.one = 0, + .ieee.mantissa = 0, +}; + +static const union float80u pos_denorm = { + .ieee.negative = 0, + .ieee.exponent = 0, + .ieee.one = 0, + .ieee.mantissa = 1, +}; + +static const union float80u smallest_positive_norm = { + .ieee.negative = 0, + .ieee.exponent = 1, + .ieee.one = 1, + .ieee.mantissa = 0, +}; + +static void fninit() +{ + asm volatile ("fninit\n"); +} + +static long double fprem(long double a, long double b, uint16_t *sw) +{ + long double result; + asm volatile ("fprem\n" + "fnstsw %1\n" + : "=t" (result), "=m" (*sw) + : "0" (a), "u" (b) + : "st(1)"); + return result; +} + +#define FPUS_IE (1 << 0) +#define FPUS_DE (1 << 1) +#define FPUS_ZE (1 << 2) +#define FPUS_OE (1 << 3) +#define FPUS_UE (1 << 4) +#define FPUS_PE (1 << 5) +#define FPUS_SF (1 << 6) +#define FPUS_SE (1 << 7) +#define FPUS_C0 (1 << 8) +#define FPUS_C1 (1 << 9) +#define FPUS_C2 (1 << 10) +#define FPUS_TOP 0x3800 +#define FPUS_C3 (1 << 14) +#define FPUS_B (1 << 15) + +#define FPUS_EMASK 0x007f + +#define FPUC_EM 0x3f + +static void psw(uint16_t sw) +{ + printf("SW: C3 TopC2C1C0\n"); + printf("SW: %c %d %3d %d %d %d %c %c %c %c %c %c %c %c\n", + sw & FPUS_B ? 'B' : 'b', + !!(sw & FPUS_C3), + (sw & FPUS_TOP) >> 11, + !!(sw & FPUS_C2), + !!(sw & FPUS_C1), + !!(sw & FPUS_C0), + (sw & FPUS_SE) ? 'S' : 's', + (sw & FPUS_SF) ? 'F' : 'f', + (sw & FPUS_PE) ? 'P' : 'p', + (sw & FPUS_UE) ? 'U' : 'u', + (sw & FPUS_OE) ? 'O' : 'o', + (sw & FPUS_ZE) ? 'Z' : 'z', + (sw & FPUS_DE) ? 'D' : 'd', + (sw & FPUS_IE) ? 'I' : 'i'); +} + +static void do_fprem(long double a, long double b) +{ + const union float80u au = {.d = a}; + const union float80u bu = {.d = b}; + union float80u ru; + uint16_t sw; + + printf("A: S=%d Exp=%04x Int=%d (QNaN=%d) Sig=%016llx (%.06Le)\n", + au.ieee.negative, au.ieee.exponent, au.ieee.one, + au.ieee_nan.quiet_nan, (unsigned long long)au.ieee.mantissa, + a); + printf("B: S=%d Exp=%04x Int=%d (QNaN=%d) Sig=%016llx (%.06Le)\n", + bu.ieee.negative, bu.ieee.exponent, bu.ieee.one, + bu.ieee_nan.quiet_nan, (unsigned long long)bu.ieee.mantissa, + b); + + fninit(); + ru.d = fprem(a, b, &sw); + psw(sw); + + printf("R: S=%d Exp=%04x Int=%d (QNaN=%d) Sig=%016llx (%.06Le)\n", + ru.ieee.negative, ru.ieee.exponent, ru.ieee.one, + ru.ieee_nan.quiet_nan, (unsigned long long)ru.ieee.mantissa, + ru.d); + printf("\n"); +} + +static void do_fprem_stack_underflow(void) +{ + const long double a = 1.0; + union float80u ru; + uint16_t sw; + + fninit(); + asm volatile ("fprem\n" + "fnstsw %1\n" + : "=t" (ru.d), "=m" (sw) + : "0" (a) + : "st(1)"); + psw(sw); + + printf("R: S=%d Exp=%04x Int=%d (QNaN=%d) Sig=%016llx (%.06Le)\n", + ru.ieee.negative, ru.ieee.exponent, ru.ieee.one, + ru.ieee_nan.quiet_nan, (unsigned long long)ru.ieee.mantissa, + ru.d); + printf("\n"); +} + +static void test_fprem_cases(void) +{ + printf("= stack underflow =\n"); + do_fprem_stack_underflow(); + + printf("= invalid operation =\n"); + do_fprem(s_nan.d, 1.0); + do_fprem(1.0, 0.0); + do_fprem(pos_inf.d, 1.0); + do_fprem(pseudo_pos_inf.d, 1.0); + + printf("= denormal =\n"); + do_fprem(pos_denorm.d, 1.0); + do_fprem(1.0, pos_denorm.d); + + /* printf("= underflow =\n"); */ + /* TODO(catalinp): Is there a case where FPREM raises underflow? */ +} + +static void test_fprem_pairs(void) +{ + unsigned int negative_index_a = 0; + unsigned int negative_index_b = 0; + static const unsigned int negative_values[] = { + 0, + 1, + }; + + unsigned int exponent_index_a = 0; + unsigned int exponent_index_b = 0; + static const unsigned int exponent_values[] = { + 0, + 1, + 2, + IEEE854_LONG_DOUBLE_BIAS - 1, + IEEE854_LONG_DOUBLE_BIAS, + IEEE854_LONG_DOUBLE_BIAS + 1, + 0x7ffd, + 0x7ffe, + 0x7fff, + }; + + unsigned int one_index_a = 0; + unsigned int one_index_b = 0; + static const unsigned int one_values[] = { + 0, + 1, + }; + + unsigned int quiet_nan_index_a = 0; + unsigned int quiet_nan_index_b = 0; + static const unsigned int quiet_nan_values[] = { + 0, + 1, + }; + + unsigned int mantissa_index_a = 0; + unsigned int mantissa_index_b = 0; + static const unsigned long long mantissa_values[] = { + 0, + 1, + 2, + 0x3ffffffffffffffdULL, + 0x3ffffffffffffffeULL, + 0x3fffffffffffffffULL, + }; + + for (;;) { +#define INIT_FIELD(var, field) \ + .ieee_nan.field = field##_values[field##_index_##var] + const union float80u a = { + INIT_FIELD(a, negative), + INIT_FIELD(a, exponent), + INIT_FIELD(a, one), + INIT_FIELD(a, quiet_nan), + INIT_FIELD(a, mantissa), + }; + const union float80u b = { + INIT_FIELD(b, negative), + INIT_FIELD(b, exponent), + INIT_FIELD(b, one), + INIT_FIELD(b, quiet_nan), + INIT_FIELD(b, mantissa), + }; +#undef INIT_FIELD + + do_fprem(a.d, b.d); + + int carry = 1; +#define CARRY_INTO(var, field) do { \ + if (carry) { \ + if (++field##_index_##var == ARRAY_SIZE(field##_values)) { \ + field##_index_##var = 0; \ + } else { \ + carry = 0; \ + } \ + } \ + } while (0) + CARRY_INTO(b, mantissa); + CARRY_INTO(b, quiet_nan); + CARRY_INTO(b, one); + CARRY_INTO(b, exponent); + CARRY_INTO(b, negative); + CARRY_INTO(a, mantissa); + CARRY_INTO(a, quiet_nan); + CARRY_INTO(a, one); + CARRY_INTO(a, exponent); + CARRY_INTO(a, negative); +#undef CARRY_INTO + + if (carry) { + break; + } + } +} + +int main(int argc, char **argv) +{ + test_fprem_cases(); + test_fprem_pairs(); + return 0; +}