From patchwork Thu Jul 12 13:36:45 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 170678 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0B5292C02BC for ; Fri, 13 Jul 2012 00:39:40 +1000 (EST) Received: from localhost ([::1]:38555 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SpJae-00047s-C4 for incoming@patchwork.ozlabs.org; Thu, 12 Jul 2012 09:37:56 -0400 Received: from eggs.gnu.org ([208.118.235.92]:43549) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SpJZu-0002iT-K1 for qemu-devel@nongnu.org; Thu, 12 Jul 2012 09:37:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SpJZs-0006pH-Nz for qemu-devel@nongnu.org; Thu, 12 Jul 2012 09:37:10 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:41606) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SpJZs-0006no-Gu for qemu-devel@nongnu.org; Thu, 12 Jul 2012 09:37:08 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SpJZg-0000U7-Dj; Thu, 12 Jul 2012 14:36:56 +0100 From: Peter Maydell To: Blue Swirl Date: Thu, 12 Jul 2012 14:36:45 +0100 Message-Id: <1342100216-1832-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1342100216-1832-1-git-send-email-peter.maydell@linaro.org> References: <1342100216-1832-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: qemu-devel@nongnu.org, Anthony Liguori , Paul Brook Subject: [Qemu-devel] [PATCH 04/15] target-arm: Fix TCG temp handling in 64 bit cp writes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Fix errors in the TCG temp handling in the 64 bit coprocessor write path: we were reusing a 32 bit temp after it had been freed by store_reg(), and failing to free a 64 bit temp. This bug has no visible effect at this point because there aren't any non-NOP 64 bit registers yet; it needs to be fixed as a prerequisite for the 64 bit registers in LPAE support. Signed-off-by: Peter Maydell --- target-arm/translate.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index f39b9ca..29008a4 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -6263,7 +6263,9 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn) tcg_gen_trunc_i64_i32(tmp, tmp64); store_reg(s, rt, tmp); tcg_gen_shri_i64(tmp64, tmp64, 32); + tmp = tcg_temp_new_i32(); tcg_gen_trunc_i64_i32(tmp, tmp64); + tcg_temp_free_i64(tmp64); store_reg(s, rt2, tmp); } else { TCGv tmp;