From patchwork Sat Jun 23 23:07:32 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 166857 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id AE1D0B6F86 for ; Sun, 24 Jun 2012 11:54:09 +1000 (EST) Received: from localhost ([::1]:37864 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Sic1f-00081U-LO for incoming@patchwork.ozlabs.org; Sat, 23 Jun 2012 21:54:07 -0400 Received: from eggs.gnu.org ([208.118.235.92]:38972) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SiZRZ-0000Tm-4I for qemu-devel@nongnu.org; Sat, 23 Jun 2012 19:08:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SiZRM-0002Zw-W0 for qemu-devel@nongnu.org; Sat, 23 Jun 2012 19:08:40 -0400 Received: from cantor2.suse.de ([195.135.220.15]:34969 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SiZRM-0002Yi-JL; Sat, 23 Jun 2012 19:08:28 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 53C9FA4479; Sun, 24 Jun 2012 01:08:27 +0200 (CEST) From: Alexander Graf To: qemu-devel qemu-devel Date: Sun, 24 Jun 2012 01:07:32 +0200 Message-Id: <1340492856-21126-69-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1340492856-21126-1-git-send-email-agraf@suse.de> References: <1340492856-21126-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: Blue Swirl , qemu-ppc Mailing List , Aurelien Jarno Subject: [Qemu-devel] [PATCH 68/72] PPC: BookE: Make ivpr selectable by CPU type X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org IVPR can either hold 32 or 64 bit addresses, depending on the CPU type. Let the CPU initialization function pass in its mask itself, so we can easily extend it. Signed-off-by: Alexander Graf --- target-ppc/translate_init.c | 9 +++++---- 1 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 57027a2..98695ab 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -2804,7 +2804,7 @@ static void init_excp_G2 (CPUPPCState *env) #endif } -static void init_excp_e200 (CPUPPCState *env) +static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) { #if !defined(CONFIG_USER_ONLY) env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; @@ -2829,7 +2829,7 @@ static void init_excp_e200 (CPUPPCState *env) env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; env->hreset_excp_prefix = 0x00000000UL; env->ivor_mask = 0x0000FFF7UL; - env->ivpr_mask = 0xFFFF0000UL; + env->ivpr_mask = ivpr_mask; /* Hardware reset vector */ env->hreset_vector = 0xFFFFFFFCUL; #endif @@ -4307,7 +4307,7 @@ static void init_proc_e200 (CPUPPCState *env) env->id_tlbs = 0; env->tlb_type = TLB_EMB; #endif - init_excp_e200(env); + init_excp_e200(env, 0xFFFF0000UL); env->dcache_line_size = 32; env->icache_line_size = 32; /* XXX: TODO: allocate internal IRQ controller */ @@ -4434,6 +4434,7 @@ static void init_proc_e500 (CPUPPCState *env, int version) { uint32_t tlbncfg[2]; uint64_t ivor_mask = 0x0000000F0000FFFFULL; + uint64_t ivpr_mask = 0xFFFF0000ULL; uint32_t l1cfg0 = 0x3800 /* 8 ways */ | 0x0020; /* 32 kb */ #if !defined(CONFIG_USER_ONLY) @@ -4575,7 +4576,7 @@ static void init_proc_e500 (CPUPPCState *env, int version) } #endif - init_excp_e200(env); + init_excp_e200(env, ivpr_mask); /* Allocate hardware IRQ controller */ ppce500_irq_init(env); }