From patchwork Wed Jun 20 20:11:50 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 166147 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 71D75B6FBC for ; Thu, 21 Jun 2012 06:26:26 +1000 (EST) Received: from localhost ([::1]:56894 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ShRTs-00041b-2J for incoming@patchwork.ozlabs.org; Wed, 20 Jun 2012 16:26:24 -0400 Received: from eggs.gnu.org ([208.118.235.92]:33123) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ShRFz-0005zI-RI for qemu-devel@nongnu.org; Wed, 20 Jun 2012 16:12:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ShRFw-0003PH-D9 for qemu-devel@nongnu.org; Wed, 20 Jun 2012 16:12:03 -0400 Received: from cantor2.suse.de ([195.135.220.15]:41562 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ShRFw-0003Om-4T; Wed, 20 Jun 2012 16:12:00 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id A8421A4A32; Wed, 20 Jun 2012 22:11:56 +0200 (CEST) From: Alexander Graf To: qemu-devel qemu-devel Date: Wed, 20 Jun 2012 22:11:50 +0200 Message-Id: <1340223111-13449-8-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1340223111-13449-1-git-send-email-agraf@suse.de> References: <1340223111-13449-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: Caraman Mihai Claudiu-B02008 , qemu-ppc Mailing List Subject: [Qemu-devel] [PATCH 7/8] PPC: Turn hardcoded reset mask into env variable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Some machines have MSR bits they reset with as enabled. Don't hardcode the logic, but let the individual core implementations save their own reset mask into an env variable. Signed-off-by: Alexander Graf --- target-ppc/cpu.h | 1 + target-ppc/translate_init.c | 14 ++++++++------ 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 652a35a..acf5816 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1043,6 +1043,7 @@ struct CPUPPCState { #if defined(TARGET_PPC64) struct ppc_segment_page_sizes sps; #endif + uint64_t reset_msr; #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) target_phys_addr_t vpa; diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 57027a2..efa05fc 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -6273,6 +6273,7 @@ static void init_proc_970 (CPUPPCState *env) env->slb_nr = 32; #endif init_excp_970(env); + env->reset_msr = (1ULL < MSR_SF); env->dcache_line_size = 128; env->icache_line_size = 128; /* Allocate hardware IRQ controller */ @@ -6375,6 +6376,7 @@ static void init_proc_970FX (CPUPPCState *env) env->slb_nr = 64; #endif init_excp_970(env); + env->reset_msr = (1ULL < MSR_SF); env->dcache_line_size = 128; env->icache_line_size = 128; /* Allocate hardware IRQ controller */ @@ -6465,6 +6467,7 @@ static void init_proc_970GX (CPUPPCState *env) env->slb_nr = 32; #endif init_excp_970(env); + env->reset_msr = (1ULL < MSR_SF); env->dcache_line_size = 128; env->icache_line_size = 128; /* Allocate hardware IRQ controller */ @@ -6555,6 +6558,7 @@ static void init_proc_970MP (CPUPPCState *env) env->slb_nr = 32; #endif init_excp_970(env); + env->reset_msr = (1ULL < MSR_SF); env->dcache_line_size = 128; env->icache_line_size = 128; /* Allocate hardware IRQ controller */ @@ -6640,6 +6644,7 @@ static void init_proc_POWER7 (CPUPPCState *env) env->slb_nr = 32; #endif init_excp_POWER7(env); + env->reset_msr = (1ULL < MSR_SF); env->dcache_line_size = 128; env->icache_line_size = 128; /* Allocate hardware IRQ controller */ @@ -6686,6 +6691,7 @@ static void init_proc_620 (CPUPPCState *env) /* Memory management */ gen_low_BATs(env); init_excp_620(env); + env->reset_msr = (1ULL < MSR_SF); env->dcache_line_size = 64; env->icache_line_size = 64; /* Allocate hardware IRQ controller */ @@ -9306,6 +9312,7 @@ static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def) env->nb_BATs = 0; env->nb_tlb = 0; env->nb_ways = 0; + env->reset_msr = 0; env->tlb_type = TLB_NONE; #endif /* Register SPR common to all PowerPC implementations */ @@ -10246,7 +10253,7 @@ static void ppc_cpu_reset(CPUState *s) pcc->parent_reset(s); - msr = (target_ulong)0; + msr = (target_ulong)env->reset_msr; if (0) { /* XXX: find a suitable condition to enable the hypervisor mode */ msr |= (target_ulong)MSR_HVB; @@ -10272,11 +10279,6 @@ static void ppc_cpu_reset(CPUState *s) } #endif env->msr = msr & env->msr_mask; -#if defined(TARGET_PPC64) - if (env->mmu_model & POWERPC_MMU_64) { - env->msr |= (1ULL << MSR_SF); - } -#endif hreg_compute_hflags(env); env->reserve_addr = (target_ulong)-1ULL; /* Be sure no exception or interrupt is pending */