From patchwork Wed Jun 20 12:26:49 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 166107 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 547FFB6FD3 for ; Thu, 21 Jun 2012 00:57:45 +1000 (EST) Received: from localhost ([::1]:59176 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ShKTr-0006iS-Gi for incoming@patchwork.ozlabs.org; Wed, 20 Jun 2012 08:57:55 -0400 Received: from eggs.gnu.org ([208.118.235.92]:39927) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ShKTA-0005Io-M5 for qemu-devel@nongnu.org; Wed, 20 Jun 2012 08:57:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ShKT4-0002Cs-9m for qemu-devel@nongnu.org; Wed, 20 Jun 2012 08:57:12 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:59525) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ShKT4-00025V-2w for qemu-devel@nongnu.org; Wed, 20 Jun 2012 08:57:06 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1ShK0H-0004KX-IZ; Wed, 20 Jun 2012 13:27:21 +0100 From: Peter Maydell To: Blue Swirl Date: Wed, 20 Jun 2012 13:26:49 +0100 Message-Id: <1340195241-16620-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1340195241-16620-1-git-send-email-peter.maydell@linaro.org> References: <1340195241-16620-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: qemu-devel@nongnu.org, Anthony Liguori , Paul Brook Subject: [Qemu-devel] [PATCH 01/33] target-arm: Fix 11MPCore cache type register value X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Make the 11MPCore report a valid value in its cache type register (the previous value appears to have been incorrectly copied from the 1136/1176). In particular, do not report that we have an aliasing VIPT cache, because this causes Linux to attempt to use the v6 block cache ops which the 11MPCore doesn't actually have. (This causes no problems currently because we over-broadly provide those ops on all cores, but prevents us correctly narrowing the block ops down to those cores which actually implement them.) Signed-off-by: Peter Maydell --- target-arm/cpu.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 7eb323a..934894b 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -307,7 +307,7 @@ static void arm11mpcore_initfn(Object *obj) cpu->reset_fpsid = 0x410120b4; cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; - cpu->ctr = 0x1dd20d2; + cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ cpu->id_pfr0 = 0x111; cpu->id_pfr1 = 0x1; cpu->id_dfr0 = 0;