From patchwork Mon Jun 4 19:37:44 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Berger X-Patchwork-Id: 162865 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 7A324B6EEC for ; Tue, 5 Jun 2012 05:43:27 +1000 (EST) Received: from localhost ([::1]:46968 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SbdBV-0001e9-C1 for incoming@patchwork.ozlabs.org; Mon, 04 Jun 2012 15:43:25 -0400 Received: from eggs.gnu.org ([208.118.235.92]:33664) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SbdB4-0000lE-M3 for qemu-devel@nongnu.org; Mon, 04 Jun 2012 15:43:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SbdB2-0000ML-T0 for qemu-devel@nongnu.org; Mon, 04 Jun 2012 15:42:58 -0400 Received: from e8.ny.us.ibm.com ([32.97.182.138]:54638) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SbdB2-0000ME-P4 for qemu-devel@nongnu.org; Mon, 04 Jun 2012 15:42:56 -0400 Received: from /spool/local by e8.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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X-Received-From: 32.97.182.138 Cc: andreas.niederl@iaik.tugraz.at, mst@redhat.com Subject: [Qemu-devel] [PATCH V19 3/7] Add a debug register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch uses the possibility to add a vendor-specific register and adds a debug register useful for dumping the TIS's internal state. This register is only active in a debug build (#define DEBUG_TIS). Signed-off-by: Stefan Berger --- hw/tpm_tis.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 70 insertions(+), 0 deletions(-) diff --git a/hw/tpm_tis.c b/hw/tpm_tis.c index 02b9c2e..5f8899d 100644 --- a/hw/tpm_tis.c +++ b/hw/tpm_tis.c @@ -52,6 +52,9 @@ #define TPM_TIS_REG_DID_VID 0xf00 #define TPM_TIS_REG_RID 0xf04 +/* vendor-specific registers */ +#define TPM_TIS_REG_DEBUG 0xf90 + #define TPM_TIS_STS_VALID (1 << 7) #define TPM_TIS_STS_COMMAND_READY (1 << 6) #define TPM_TIS_STS_TPM_GO (1 << 5) @@ -97,6 +100,11 @@ #define TPM_TIS_NO_DATA_BYTE 0xff +/* local prototypes */ + +static uint64_t tpm_tis_mmio_read(void *opaque, target_phys_addr_t addr, + unsigned size); + /* utility functions */ static uint8_t tpm_tis_locality_from_addr(target_phys_addr_t addr) @@ -331,6 +339,63 @@ static uint32_t tpm_tis_data_read(TPMState *s, uint8_t locty) return ret; } +#ifdef DEBUG_TIS +static void tpm_tis_dump_state(void *opaque, target_phys_addr_t addr) +{ + static const unsigned regs[] = { + TPM_TIS_REG_ACCESS, + TPM_TIS_REG_INT_ENABLE, + TPM_TIS_REG_INT_VECTOR, + TPM_TIS_REG_INT_STATUS, + TPM_TIS_REG_INTF_CAPABILITY, + TPM_TIS_REG_STS, + TPM_TIS_REG_DID_VID, + TPM_TIS_REG_RID, + 0xfff}; + int idx; + uint8_t locty = tpm_tis_locality_from_addr(addr); + target_phys_addr_t base = addr & ~0xfff; + TPMState *s = opaque; + TPMTISState *tis = &s->s.tis; + + dprintf("tpm_tis: active locality : %d\n" + "tpm_tis: state of locality %d : %d\n" + "tpm_tis: register dump:\n", + tis->active_locty, + locty, tis->loc[locty].status); + + for (idx = 0; regs[idx] != 0xfff; idx++) { + dprintf("tpm_tis: 0x%04x : 0x%08x\n", regs[idx], + (uint32_t)tpm_tis_mmio_read(opaque, base + regs[idx], 4)); + } + + dprintf("tpm_tis: read offset : %d\n" + "tpm_tis: result buffer : ", + tis->loc[locty].r_offset); + for (idx = 0; + idx < tpm_tis_get_size_from_buffer(&tis->loc[locty].r_buffer); + idx++) { + dprintf("%c%02x%s", + tis->loc[locty].r_offset == idx ? '>' : ' ', + tis->loc[locty].r_buffer.buffer[idx], + ((idx & 0xf) == 0xf) ? "\ntpm_tis: " : ""); + } + dprintf("\n" + "tpm_tis: write offset : %d\n" + "tpm_tis: request buffer: ", + tis->loc[locty].w_offset); + for (idx = 0; + idx < tpm_tis_get_size_from_buffer(&tis->loc[locty].w_buffer); + idx++) { + dprintf("%c%02x%s", + tis->loc[locty].w_offset == idx ? '>' : ' ', + tis->loc[locty].w_buffer.buffer[idx], + ((idx & 0xf) == 0xf) ? "\ntpm_tis: " : ""); + } + dprintf("\n"); +} +#endif + /* * Read a register of the TIS interface * See specs pages 33-63 for description of the registers @@ -400,6 +465,11 @@ static uint64_t tpm_tis_mmio_read(void *opaque, target_phys_addr_t addr, case TPM_TIS_REG_RID: val = TPM_TIS_TPM_RID; break; +#ifdef DEBUG_TIS + case TPM_TIS_REG_DEBUG: + tpm_tis_dump_state(opaque, addr); + break; +#endif } if (shift) {