From patchwork Mon May 21 16:11:06 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Chouteau X-Patchwork-Id: 160388 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3B55EB6F9A for ; Tue, 22 May 2012 02:11:42 +1000 (EST) Received: from localhost ([::1]:37195 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SWVCt-0001i8-C6 for incoming@patchwork.ozlabs.org; Mon, 21 May 2012 12:11:39 -0400 Received: from eggs.gnu.org ([208.118.235.92]:45887) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SWVCj-0001h2-KI for qemu-devel@nongnu.org; Mon, 21 May 2012 12:11:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SWVCe-0000Fw-NG for qemu-devel@nongnu.org; Mon, 21 May 2012 12:11:29 -0400 Received: from mel.act-europe.fr ([194.98.77.210]:46400) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SWVCe-0000Ff-Gi; Mon, 21 May 2012 12:11:24 -0400 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 76C49290041; Mon, 21 May 2012 18:11:27 +0200 (CEST) X-Virus-Scanned: amavisd-new at eu.adacore.com Received: from mel.act-europe.fr ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id t0ie3aKH2qlS; Mon, 21 May 2012 18:11:27 +0200 (CEST) Received: from PomPomGalli.act-europe.fr (pompomgalli.act-europe.fr [10.10.1.88]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mel.act-europe.fr (Postfix) with ESMTP id 59F5229000D; Mon, 21 May 2012 18:11:27 +0200 (CEST) From: Fabien Chouteau To: qemu-devel@nongnu.org Date: Mon, 21 May 2012 18:11:06 +0200 Message-Id: <1337616666-7503-1-git-send-email-chouteau@adacore.com> X-Mailer: git-send-email 1.7.9.5 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 194.98.77.210 Cc: qemu-ppc@nongnu.org, agraf@suse.de Subject: [Qemu-devel] [PATCH V2] booke_206_tlbwe: Discard invalid bits in MAS2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The size of EPN field in MAS2 depends on page size. This patch adds a mask to discard invalid bits in EPN field. Definition of EPN field from e500v2 RM: EPN Effective page number: Depending on page size, only the bits associated with a page boundary are valid. Bits that represent offsets within a page are ignored and should be cleared. There is a similar (but more complicated) definition in PowerISA V2.06. Signed-off-by: Fabien Chouteau --- target-ppc/op_helper.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c index 4ef2332..481b51c 100644 --- a/target-ppc/op_helper.c +++ b/target-ppc/op_helper.c @@ -4227,6 +4227,8 @@ void helper_booke206_tlbwe(void) uint32_t tlbncfg, tlbn; ppcmas_tlb_t *tlb; uint32_t size_tlb, size_ps; + target_ulong mask; + switch (env->spr[SPR_BOOKE_MAS0] & MAS0_WQ_MASK) { case MAS0_WQ_ALWAYS: @@ -4289,8 +4291,19 @@ void helper_booke206_tlbwe(void) tlb->mas1 |= (tlbncfg & TLBnCFG_MINSIZE) >> 12; } - /* XXX needs to change when supporting 64-bit e500 */ - tlb->mas2 = env->spr[SPR_BOOKE_MAS2] & 0xffffffff; + /* Make a mask from TLB size to discard invalid bits in EPN field */ + mask = ~(booke206_tlb_to_page_size(env, tlb) - 1); + /* Add a mask for page attributes */ + mask |= MAS2_ACM | MAS2_VLE | MAS2_W | MAS2_I | MAS2_M | MAS2_G | MAS2_E; + + if (!msr_cm) { + /* Executing a tlbwe instruction in 32-bit mode will set + * bits 0:31 of the TLB EPN field to zero. + */ + mask &= 0xffffffff; + } + + tlb->mas2 = env->spr[SPR_BOOKE_MAS2] & mask; if (!(tlbncfg & TLBnCFG_IPROT)) { /* no IPROT supported by TLB */