From patchwork Fri May 18 16:02:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 160133 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 6D5BEB6FBB for ; Sat, 19 May 2012 02:02:44 +1000 (EST) Received: from localhost ([::1]:41466 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SVPdY-00062H-Mb for incoming@patchwork.ozlabs.org; Fri, 18 May 2012 12:02:40 -0400 Received: from eggs.gnu.org ([208.118.235.92]:50682) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SVPdA-0005t4-4R for qemu-devel@nongnu.org; Fri, 18 May 2012 12:02:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SVPd6-0007BF-NF for qemu-devel@nongnu.org; Fri, 18 May 2012 12:02:15 -0400 Received: from cantor2.suse.de ([195.135.220.15]:48405 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SVPd6-0007Ai-A9 for qemu-devel@nongnu.org; Fri, 18 May 2012 12:02:12 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 7A857978B8; Fri, 18 May 2012 18:02:09 +0200 (CEST) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Fri, 18 May 2012 18:02:00 +0200 Message-Id: <1337356920-30784-4-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1337356920-30784-1-git-send-email-afaerber@suse.de> References: <1337356920-30784-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: peter.maydell@linaro.org, Igor Mitsyanko , Mark Langsdorf , Evgeny Voevodin , Peter Crosthwaite , Jan Kiszka , Dmitry Solodkiy , Maksim Kozlov , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [Qemu-devel] [PATCH qom-next v2 3/3] arm_pic: Pass ARMCPU to arm_pic_init_cpu() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Pass it through to arm_pic_cpu_handler(). Signed-off-by: Andreas Färber Acked-by: Peter Maydell Acked-by: Igor Mitsyanko (for exynos) --- hw/arm-misc.h | 2 +- hw/arm_pic.c | 8 +++++--- hw/armv7m.c | 2 +- hw/exynos4210.c | 3 ++- hw/highbank.c | 5 ++--- hw/integratorcp.c | 2 +- hw/musicpal.c | 2 +- hw/omap1.c | 2 +- hw/omap2.c | 2 +- hw/realview.c | 2 +- hw/strongarm.c | 2 +- hw/versatilepb.c | 2 +- hw/vexpress.c | 4 ++-- hw/xilinx_zynq.c | 2 +- 14 files changed, 21 insertions(+), 19 deletions(-) diff --git a/hw/arm-misc.h b/hw/arm-misc.h index b7f4c32..1d51570 100644 --- a/hw/arm-misc.h +++ b/hw/arm-misc.h @@ -16,7 +16,7 @@ /* The CPU is also modeled as an interrupt controller. */ #define ARM_PIC_CPU_IRQ 0 #define ARM_PIC_CPU_FIQ 1 -qemu_irq *arm_pic_init_cpu(CPUARMState *env); +qemu_irq *arm_pic_init_cpu(ARMCPU *cpu); /* armv7m.c */ qemu_irq *armv7m_init(MemoryRegion *address_space_mem, diff --git a/hw/arm_pic.c b/hw/arm_pic.c index 1094965..ffb4d41 100644 --- a/hw/arm_pic.c +++ b/hw/arm_pic.c @@ -13,7 +13,9 @@ /* Input 0 is IRQ and input 1 is FIQ. */ static void arm_pic_cpu_handler(void *opaque, int irq, int level) { - CPUARMState *env = (CPUARMState *)opaque; + ARMCPU *cpu = opaque; + CPUARMState *env = &cpu->env; + switch (irq) { case ARM_PIC_CPU_IRQ: if (level) @@ -32,7 +34,7 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level) } } -qemu_irq *arm_pic_init_cpu(CPUARMState *env) +qemu_irq *arm_pic_init_cpu(ARMCPU *cpu) { - return qemu_allocate_irqs(arm_pic_cpu_handler, env, 2); + return qemu_allocate_irqs(arm_pic_cpu_handler, cpu, 2); } diff --git a/hw/armv7m.c b/hw/armv7m.c index 418139a..8cec78d 100644 --- a/hw/armv7m.c +++ b/hw/armv7m.c @@ -215,7 +215,7 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem, nvic = qdev_create(NULL, "armv7m_nvic"); env->nvic = nvic; qdev_init_nofail(nvic); - cpu_pic = arm_pic_init_cpu(env); + cpu_pic = arm_pic_init_cpu(cpu); sysbus_connect_irq(sysbus_from_qdev(nvic), 0, cpu_pic[ARM_PIC_CPU_IRQ]); for (i = 0; i < 64; i++) { pic[i] = qdev_get_gpio_in(nvic, i); diff --git a/hw/exynos4210.c b/hw/exynos4210.c index 7dc3787..dd14d01 100644 --- a/hw/exynos4210.c +++ b/hw/exynos4210.c @@ -112,8 +112,9 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem, fprintf(stderr, "Unable to find CPU %d definition\n", n); exit(1); } + /* Create PIC controller for each processor instance */ - irqp = arm_pic_init_cpu(&s->cpu[n]->env); + irqp = arm_pic_init_cpu(s->cpu[n]); /* * Get GICs gpio_in cpu_irq to connect a combiner to them later. diff --git a/hw/highbank.c b/hw/highbank.c index a3901b0..4bdea5d 100644 --- a/hw/highbank.c +++ b/hw/highbank.c @@ -192,7 +192,6 @@ static void highbank_init(ram_addr_t ram_size, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { - CPUARMState *env = NULL; DeviceState *dev; SysBusDevice *busdev; qemu_irq *irqp; @@ -215,10 +214,10 @@ static void highbank_init(ram_addr_t ram_size, fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } - env = &cpu->env; + /* This will become a QOM property eventually */ cpu->reset_cbar = GIC_BASE_ADDR; - irqp = arm_pic_init_cpu(env); + irqp = arm_pic_init_cpu(cpu); cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; } diff --git a/hw/integratorcp.c b/hw/integratorcp.c index e927012..deacbf4 100644 --- a/hw/integratorcp.c +++ b/hw/integratorcp.c @@ -476,7 +476,7 @@ static void integratorcp_init(ram_addr_t ram_size, qdev_init_nofail(dev); sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); - cpu_pic = arm_pic_init_cpu(&cpu->env); + cpu_pic = arm_pic_init_cpu(cpu); dev = sysbus_create_varargs("integrator_pic", 0x14000000, cpu_pic[ARM_PIC_CPU_IRQ], cpu_pic[ARM_PIC_CPU_FIQ], NULL); diff --git a/hw/musicpal.c b/hw/musicpal.c index cef847e..f14f20d 100644 --- a/hw/musicpal.c +++ b/hw/musicpal.c @@ -1538,7 +1538,7 @@ static void musicpal_init(ram_addr_t ram_size, fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } - cpu_pic = arm_pic_init_cpu(&cpu->env); + cpu_pic = arm_pic_init_cpu(cpu); /* For now we use a fixed - the original - RAM size */ memory_region_init_ram(ram, "musicpal.ram", MP_RAM_DEFAULT_SIZE); diff --git a/hw/omap1.c b/hw/omap1.c index a997d30..ad60cc4 100644 --- a/hw/omap1.c +++ b/hw/omap1.c @@ -3854,7 +3854,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s); - cpu_irq = arm_pic_init_cpu(&s->cpu->env); + cpu_irq = arm_pic_init_cpu(s->cpu); s->ih[0] = qdev_create(NULL, "omap-intc"); qdev_prop_set_uint32(s->ih[0], "size", 0x100); qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck")); diff --git a/hw/omap2.c b/hw/omap2.c index 196c4b6..4278dd1 100644 --- a/hw/omap2.c +++ b/hw/omap2.c @@ -2277,7 +2277,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54); /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */ - cpu_irq = arm_pic_init_cpu(&s->cpu->env); + cpu_irq = arm_pic_init_cpu(s->cpu); s->ih[0] = qdev_create(NULL, "omap2-intc"); qdev_prop_set_uint8(s->ih[0], "revision", 0x21); qdev_prop_set_ptr(s->ih[0], "fclk", omap_findclk(s, "mpu_intc_fclk")); diff --git a/hw/realview.c b/hw/realview.c index 38085f1..19db4d0 100644 --- a/hw/realview.c +++ b/hw/realview.c @@ -94,7 +94,7 @@ static void realview_init(ram_addr_t ram_size, fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } - irqp = arm_pic_init_cpu(&cpu->env); + irqp = arm_pic_init_cpu(cpu); cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; } env = &cpu->env; diff --git a/hw/strongarm.c b/hw/strongarm.c index 38b1d0c..7150eeb 100644 --- a/hw/strongarm.c +++ b/hw/strongarm.c @@ -1574,7 +1574,7 @@ StrongARMState *sa1110_init(MemoryRegion *sysmem, vmstate_register_ram_global(&s->sdram); memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram); - pic = arm_pic_init_cpu(&s->cpu->env); + pic = arm_pic_init_cpu(s->cpu); s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000, pic[ARM_PIC_CPU_IRQ], pic[ARM_PIC_CPU_FIQ], NULL); diff --git a/hw/versatilepb.c b/hw/versatilepb.c index ed54fdd..4fd5d9b 100644 --- a/hw/versatilepb.c +++ b/hw/versatilepb.c @@ -209,7 +209,7 @@ static void versatile_init(ram_addr_t ram_size, qdev_init_nofail(sysctl); sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000); - cpu_pic = arm_pic_init_cpu(&cpu->env); + cpu_pic = arm_pic_init_cpu(cpu); dev = sysbus_create_varargs("pl190", 0x10140000, cpu_pic[0], cpu_pic[1], NULL); for (n = 0; n < 32; n++) { diff --git a/hw/vexpress.c b/hw/vexpress.c index 4797c6a..8072c5a 100644 --- a/hw/vexpress.c +++ b/hw/vexpress.c @@ -181,7 +181,7 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard, fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } - irqp = arm_pic_init_cpu(&cpu->env); + irqp = arm_pic_init_cpu(cpu); cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; } @@ -280,7 +280,7 @@ static void a15_daughterboard_init(const VEDBoardInfo *daughterboard, fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } - irqp = arm_pic_init_cpu(&cpu->env); + irqp = arm_pic_init_cpu(cpu); cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; } diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c index 11026cb..7e6c273 100644 --- a/hw/xilinx_zynq.c +++ b/hw/xilinx_zynq.c @@ -71,7 +71,7 @@ static void zynq_init(ram_addr_t ram_size, const char *boot_device, fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } - irqp = arm_pic_init_cpu(&cpu->env); + irqp = arm_pic_init_cpu(cpu); cpu_irq = irqp[ARM_PIC_CPU_IRQ]; /* max 2GB ram */