From patchwork Mon May 14 19:03:17 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 159127 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A3417B702E for ; Tue, 15 May 2012 05:28:54 +1000 (EST) Received: from localhost ([::1]:32915 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SU0wu-0006OB-Ft for incoming@patchwork.ozlabs.org; Mon, 14 May 2012 15:28:52 -0400 Received: from eggs.gnu.org ([208.118.235.92]:33882) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SU0v9-0004E4-O1 for qemu-devel@nongnu.org; Mon, 14 May 2012 15:27:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SU0v6-000371-GU for qemu-devel@nongnu.org; Mon, 14 May 2012 15:27:03 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:34238) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SU0v6-00030M-7o for qemu-devel@nongnu.org; Mon, 14 May 2012 15:27:00 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SU0YP-0005nO-JU; Mon, 14 May 2012 20:03:33 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 14 May 2012 20:03:17 +0100 Message-Id: <1337022212-22219-19-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> References: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: Rusty Russell , Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= , patches@linaro.org Subject: [Qemu-devel] [PATCH qom-next v2 18/33] target-arm: Convert cp15 crn=10 registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We RAZ/WI the entire block of crn=10 registers. Note that this actually covers not just the implementation-defined TLB lockdown registers but also a number of v7 VMSA memory attribute registers which we would need to implement to support TEX remap. We retain the previous QEMU behaviour in this conversion, though. Signed-off-by: Peter Maydell --- target-arm/helper.c | 11 +++++------ 1 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index c19ba9e..e83f1c8 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -111,6 +111,11 @@ static const ARMCPRegInfo cp_reginfo[] = { { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse), .resetvalue = 0, .writefn = contextidr_write }, + /* ??? This covers not just the impdef TLB lockdown registers but also + * some v7VMSA registers relating to TEX remap, so it is overly broad. + */ + { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY, + .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, REGINFO_SENTINEL }; @@ -1800,9 +1805,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) goto bad_reg; } break; - case 10: /* MMU TLB lockdown. */ - /* ??? TLB lockdown not implemented. */ - break; case 12: /* Reserved. */ goto bad_reg; case 15: /* Implementation specific. */ @@ -2080,9 +2082,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) goto bad_reg; } break; - case 10: /* MMU TLB lockdown. */ - /* ??? TLB lockdown not implemented. */ - return 0; case 11: /* TCM DMA control. */ case 12: /* Reserved. */ goto bad_reg;