From patchwork Wed May 2 17:12:04 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 156515 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1E542B6FA8 for ; Thu, 3 May 2012 03:25:29 +1000 (EST) Received: from localhost ([::1]:45458 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SPd77-0004jv-9r for incoming@patchwork.ozlabs.org; Wed, 02 May 2012 13:13:17 -0400 Received: from eggs.gnu.org ([208.118.235.92]:55737) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SPd6L-0002Cj-1j for qemu-devel@nongnu.org; Wed, 02 May 2012 13:12:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SPd6H-0002W6-QN for qemu-devel@nongnu.org; Wed, 02 May 2012 13:12:28 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:33531) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SPd6H-0002UL-I2 for qemu-devel@nongnu.org; Wed, 02 May 2012 13:12:25 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SPd65-0008Te-3D; Wed, 02 May 2012 18:12:13 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Wed, 2 May 2012 18:12:04 +0100 Message-Id: <1335978732-32559-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1335978732-32559-1-git-send-email-peter.maydell@linaro.org> References: <1335978732-32559-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= , patches@linaro.org Subject: [Qemu-devel] [PATCH 1/9] hw/arm_gic: Remove NVIC ifdefs from gic_state struct X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Remove some NVIC ifdefs from the gic_state struct and its state save/load functions. This means there are some fields in it which are present for the NVIC but not used, but means it always has the same layout and can be pulled out into a common subclass. Note that the addition of irq_target[] to the save/load struct for the NVIC requires a vmstate version bump. Signed-off-by: Peter Maydell Reviewed-by: Andreas Färber --- hw/arm_gic.c | 15 +++------------ 1 files changed, 3 insertions(+), 12 deletions(-) diff --git a/hw/arm_gic.c b/hw/arm_gic.c index 72298b4..17b2eba 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -108,9 +108,7 @@ typedef struct gic_state int cpu_enabled[NCPU]; gic_irq_state irq_state[GIC_MAXIRQ]; -#ifndef NVIC int irq_target[GIC_MAXIRQ]; -#endif int priority1[GIC_INTERNAL][NCPU]; int priority2[GIC_MAXIRQ - GIC_INTERNAL]; int last_active[GIC_MAXIRQ][NCPU]; @@ -120,18 +118,14 @@ typedef struct gic_state int running_priority[NCPU]; int current_pending[NCPU]; -#if NCPU > 1 uint32_t num_cpu; -#endif MemoryRegion iomem; /* Distributor */ -#ifndef NVIC /* This is just so we can have an opaque pointer which identifies * both this GIC and which CPU interface we should be accessing. */ struct gic_state *backref[NCPU]; MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */ -#endif uint32_t num_irq; } gic_state; @@ -800,9 +794,7 @@ static void gic_save(QEMUFile *f, void *opaque) qemu_put_be32(f, s->priority2[i]); } for (i = 0; i < s->num_irq; i++) { -#ifndef NVIC qemu_put_be32(f, s->irq_target[i]); -#endif qemu_put_byte(f, s->irq_state[i].enabled); qemu_put_byte(f, s->irq_state[i].pending); qemu_put_byte(f, s->irq_state[i].active); @@ -818,8 +810,9 @@ static int gic_load(QEMUFile *f, void *opaque, int version_id) int i; int j; - if (version_id != 2) + if (version_id != 3) { return -EINVAL; + } s->enabled = qemu_get_be32(f); for (i = 0; i < NUM_CPU(s); i++) { @@ -837,9 +830,7 @@ static int gic_load(QEMUFile *f, void *opaque, int version_id) s->priority2[i] = qemu_get_be32(f); } for (i = 0; i < s->num_irq; i++) { -#ifndef NVIC s->irq_target[i] = qemu_get_be32(f); -#endif s->irq_state[i].enabled = qemu_get_byte(f); s->irq_state[i].pending = qemu_get_byte(f); s->irq_state[i].active = qemu_get_byte(f); @@ -914,7 +905,7 @@ static void gic_init(gic_state *s, int num_irq) } #endif - register_savevm(NULL, "arm_gic", -1, 2, gic_save, gic_load, s); + register_savevm(NULL, "arm_gic", -1, 3, gic_save, gic_load, s); } #ifndef NVIC