diff mbox

[1/2] pc: add pci64 memory hole

Message ID 1335967335-30197-2-git-send-email-kraxel@redhat.com
State New
Headers show

Commit Message

Gerd Hoffmann May 2, 2012, 2:02 p.m. UTC 
This patch adds a address space hole for 64bit PCI ressources.
It starts at 0x8000000000 (512 GB) and ends at 0x10000000000 (1 TB),
thus has 512 GB in size.  This matches what the seabios is doing
(latest master branch).

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
 hw/pc.c      |   17 ++++++++++++++---
 hw/pc.h      |    6 ++++++
 hw/pc_piix.c |   22 ++++++++++------------
 3 files changed, 30 insertions(+), 15 deletions(-)

Comments

Avi Kivity May 2, 2012, 3:31 p.m. UTC | #1 
On 05/02/2012 05:02 PM, Gerd Hoffmann wrote:
> This patch adds a address space hole for 64bit PCI ressources.
> It starts at 0x8000000000 (512 GB) and ends at 0x10000000000 (1 TB),
> thus has 512 GB in size.  This matches what the seabios is doing
> (latest master branch).

We should communicate this to seabios via fwcfg (really seabios should
communicate this to the chipset, but our chipset doesn't support this at
all).

It should also only apply to -M old.
Gerd Hoffmann May 2, 2012, 3:46 p.m. UTC | #2 
On 05/02/12 17:31, Avi Kivity wrote:
> On 05/02/2012 05:02 PM, Gerd Hoffmann wrote:
>> This patch adds a address space hole for 64bit PCI ressources.
>> It starts at 0x8000000000 (512 GB) and ends at 0x10000000000 (1 TB),
>> thus has 512 GB in size.  This matches what the seabios is doing
>> (latest master branch).
> 
> We should communicate this to seabios via fwcfg

A dsdt entry is needed for the pci64 window (see
http://code.coreboot.org/p/seabios/source/commit/482a020ec25f4cec655ddcb16b67c6f38b0844c0/),
which makes it non-trivial to turn this into a runtime option ...

> It should also only apply to -M old.

Is this the only reason you want this be runtime-switchable?

cheers,
  Gerd
Avi Kivity May 2, 2012, 3:52 p.m. UTC | #3 
On 05/02/2012 06:46 PM, Gerd Hoffmann wrote:
> On 05/02/12 17:31, Avi Kivity wrote:
> > On 05/02/2012 05:02 PM, Gerd Hoffmann wrote:
> >> This patch adds a address space hole for 64bit PCI ressources.
> >> It starts at 0x8000000000 (512 GB) and ends at 0x10000000000 (1 TB),
> >> thus has 512 GB in size.  This matches what the seabios is doing
> >> (latest master branch).
> > 
> > We should communicate this to seabios via fwcfg
>
> A dsdt entry is needed for the pci64 window (see
> http://code.coreboot.org/p/seabios/source/commit/482a020ec25f4cec655ddcb16b67c6f38b0844c0/),
> which makes it non-trivial to turn this into a runtime option ...

It's a function, isn't it?  So all you need is a ASL driver for fwcfg
and an If().

> > It should also only apply to -M old.
>
> Is this the only reason you want this be runtime-switchable?

No.  The BIOS and qemu shouldn't be making too many assumptions. 
Certainly for Q35 we'd have the bios program qemu for the 64 bit hole.
diff mbox

Patch

diff --git a/hw/pc.c b/hw/pc.c
index 4d34a33..de1b297 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -981,12 +981,13 @@  void pc_memory_init(MemoryRegion *system_memory,
                     const char *initrd_filename,
                     ram_addr_t below_4g_mem_size,
                     ram_addr_t above_4g_mem_size,
+                    ram_addr_t above_1t_mem_size,
                     MemoryRegion *rom_memory,
                     MemoryRegion **ram_memory)
 {
     int linux_boot, i;
     MemoryRegion *ram, *option_rom_mr;
-    MemoryRegion *ram_below_4g, *ram_above_4g;
+    MemoryRegion *ram_below_4g, *ram_above_4g, *ram_above_1t;
     void *fw_cfg;
 
     linux_boot = (kernel_filename != NULL);
@@ -997,7 +998,9 @@  void pc_memory_init(MemoryRegion *system_memory,
      */
     ram = g_malloc(sizeof(*ram));
     memory_region_init_ram(ram, "pc.ram",
-                           below_4g_mem_size + above_4g_mem_size);
+                           below_4g_mem_size +
+                           above_4g_mem_size +
+                           above_1t_mem_size);
     vmstate_register_ram_global(ram);
     *ram_memory = ram;
     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
@@ -1008,9 +1011,17 @@  void pc_memory_init(MemoryRegion *system_memory,
         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
         memory_region_init_alias(ram_above_4g, "ram-above-4g", ram,
                                  below_4g_mem_size, above_4g_mem_size);
-        memory_region_add_subregion(system_memory, 0x100000000ULL,
+        memory_region_add_subregion(system_memory, PCI_HOLE_END,
                                     ram_above_4g);
     }
+    if (above_1t_mem_size > 0) {
+        ram_above_1t = g_malloc(sizeof(*ram_above_1t));
+        memory_region_init_alias(ram_above_1t, "ram-above-1t", ram,
+                                 below_4g_mem_size + above_4g_mem_size,
+                                 above_1t_mem_size);
+        memory_region_add_subregion(system_memory, PCI_HOLE64_END,
+                                    ram_above_1t);
+    }
 
 
     /* Initialize PC system firmware */
diff --git a/hw/pc.h b/hw/pc.h
index 74d3369..0c5e14e 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -12,6 +12,11 @@ 
 
 /* PC-style peripherals (also used by other machines).  */
 
+#define PCI_HOLE_START   0x0000e0000000ULL
+#define PCI_HOLE_END     0x000100000000ULL
+#define PCI_HOLE64_START 0x008000000000ULL
+#define PCI_HOLE64_END   0x010000000000ULL
+
 /* serial.c */
 
 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
@@ -112,6 +117,7 @@  void pc_memory_init(MemoryRegion *system_memory,
                     const char *initrd_filename,
                     ram_addr_t below_4g_mem_size,
                     ram_addr_t above_4g_mem_size,
+                    ram_addr_t above_1t_mem_size,
                     MemoryRegion *rom_memory,
                     MemoryRegion **ram_memory);
 qemu_irq *pc_allocate_cpu_irq(void);
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index 6a75718..27f990f 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -133,7 +133,7 @@  static void pc_init1(MemoryRegion *system_memory,
                      int kvmclock_enabled)
 {
     int i;
-    ram_addr_t below_4g_mem_size, above_4g_mem_size;
+    ram_addr_t below_4g_mem_size, above_4g_mem_size, above_1t_mem_size;
     PCIBus *pci_bus;
     ISABus *isa_bus;
     PCII440FXState *i440fx_state;
@@ -157,13 +157,10 @@  static void pc_init1(MemoryRegion *system_memory,
         kvmclock_create();
     }
 
-    if (ram_size >= 0xe0000000 ) {
-        above_4g_mem_size = ram_size - 0xe0000000;
-        below_4g_mem_size = 0xe0000000;
-    } else {
-        above_4g_mem_size = 0;
-        below_4g_mem_size = ram_size;
-    }
+    below_4g_mem_size = MIN(ram_size, PCI_HOLE_START);
+    above_4g_mem_size = MIN(ram_size - below_4g_mem_size,
+                            PCI_HOLE64_START - PCI_HOLE_END);
+    above_1t_mem_size = ram_size - below_4g_mem_size - above_4g_mem_size;
 
     if (pci_enabled) {
         pci_memory = g_new(MemoryRegion, 1);
@@ -178,7 +175,7 @@  static void pc_init1(MemoryRegion *system_memory,
     if (!xen_enabled()) {
         pc_memory_init(system_memory,
                        kernel_filename, kernel_cmdline, initrd_filename,
-                       below_4g_mem_size, above_4g_mem_size,
+                       below_4g_mem_size, above_4g_mem_size, above_1t_mem_size,
                        pci_enabled ? rom_memory : system_memory, &ram_memory);
     }
 
@@ -195,11 +192,12 @@  static void pc_init1(MemoryRegion *system_memory,
         pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, &isa_bus, gsi,
                               system_memory, system_io, ram_size,
                               below_4g_mem_size,
-                              0x100000000ULL - below_4g_mem_size,
-                              0x100000000ULL + above_4g_mem_size,
+                              PCI_HOLE_END - below_4g_mem_size,
+                              PCI_HOLE_END + above_4g_mem_size,
                               (sizeof(target_phys_addr_t) == 4
                                ? 0
-                               : ((uint64_t)1 << 62)),
+                               : (PCI_HOLE64_END - PCI_HOLE_END -
+                                  above_4g_mem_size)),
                               pci_memory, ram_memory);
     } else {
         pci_bus = NULL;