From patchwork Sat Apr 14 20:48:37 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Herv=C3=A9_Poussineau?= X-Patchwork-Id: 152553 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E284CB6FC4 for ; Sun, 15 Apr 2012 06:49:25 +1000 (EST) Received: from localhost ([::1]:53976 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SJ9uN-00029b-Ov for incoming@patchwork.ozlabs.org; Sat, 14 Apr 2012 16:49:23 -0400 Received: from eggs.gnu.org ([208.118.235.92]:45073) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SJ9u9-0001wJ-AR for qemu-devel@nongnu.org; Sat, 14 Apr 2012 16:49:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SJ9u7-00041r-2s for qemu-devel@nongnu.org; Sat, 14 Apr 2012 16:49:08 -0400 Received: from smtp1-g21.free.fr ([212.27.42.1]:51000) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SJ9u6-0003xB-FK; Sat, 14 Apr 2012 16:49:07 -0400 Received: from localhost.localdomain (unknown [82.227.227.196]) by smtp1-g21.free.fr (Postfix) with ESMTP id A8C629400FD; Sat, 14 Apr 2012 22:48:59 +0200 (CEST) From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= To: qemu-devel@nongnu.org Date: Sat, 14 Apr 2012 22:48:37 +0200 Message-Id: <1334436519-3393-5-git-send-email-hpoussin@reactos.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1334436519-3393-1-git-send-email-hpoussin@reactos.org> References: <1334436519-3393-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 212.27.42.1 Cc: =?UTF-8?q?Herv=C3=A9=20Poussineau?= , qemu-ppc@nongnu.org Subject: [Qemu-devel] [PATCH v2 4/6] prep: move int-ack register from PReP to Raven PCI emulation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Register is one byte-wide (as per specification), so there is no need to specify endianness. Signed-off-by: Hervé Poussineau --- hw/ppc_prep.c | 36 ------------------------------------ hw/prep_pci.c | 14 ++++++++++++++ 2 files changed, 14 insertions(+), 36 deletions(-) diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c index 30029f9..6a0d81d 100644 --- a/hw/ppc_prep.c +++ b/hw/ppc_prep.c @@ -85,38 +85,6 @@ static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; /* ISA IO ports bridge */ #define PPC_IO_BASE 0x80000000 -/* PCI intack register */ -/* Read-only register (?) */ -static void PPC_intack_write (void *opaque, target_phys_addr_t addr, - uint64_t value, unsigned size) -{ -#if 0 - printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx64 "\n", __func__, addr, - value); -#endif -} - -static uint64_t PPC_intack_read(void *opaque, target_phys_addr_t addr, - unsigned size) -{ - uint32_t retval = 0; - - if ((addr & 0xf) == 0) - retval = pic_read_irq(isa_pic); -#if 0 - printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, - retval); -#endif - - return retval; -} - -static const MemoryRegionOps PPC_intack_ops = { - .read = PPC_intack_read, - .write = PPC_intack_write, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - /* PowerPC control and status registers */ #if 0 // Not used static struct { @@ -472,7 +440,6 @@ static void ppc_prep_init (ram_addr_t ram_size, nvram_t nvram; M48t59State *m48t59; MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1); - MemoryRegion *intack = g_new(MemoryRegion, 1); #if 0 MemoryRegion *xcsr = g_new(MemoryRegion, 1); #endif @@ -658,9 +625,6 @@ static void ppc_prep_init (ram_addr_t ram_size, register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl); register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); - /* PCI intack location */ - memory_region_init_io(intack, &PPC_intack_ops, NULL, "ppc-intack", 4); - memory_region_add_subregion(sysmem, 0xBFFFFFF0, intack); /* PowerPC control and status register group */ #if 0 memory_region_init_io(xcsr, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000); diff --git a/hw/prep_pci.c b/hw/prep_pci.c index 8b29da9..43847f5 100644 --- a/hw/prep_pci.c +++ b/hw/prep_pci.c @@ -25,10 +25,12 @@ #include "hw.h" #include "pci.h" #include "pci_host.h" +#include "pc.h" #include "exec-memory.h" typedef struct PRePPCIState { PCIHostState host_state; + MemoryRegion intack; qemu_irq irq[4]; } PREPPCIState; @@ -67,6 +69,16 @@ static const MemoryRegionOps PPC_PCIIO_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; +static uint64_t ppc_intack_read(void *opaque, target_phys_addr_t addr, + unsigned int size) +{ + return pic_read_irq(isa_pic); +} + +static const MemoryRegionOps PPC_intack_ops = { + .read = ppc_intack_read, +}; + static int prep_map_irq(PCIDevice *pci_dev, int irq_num) { return (irq_num + (pci_dev->devfn >> 3)) & 1; @@ -110,6 +122,8 @@ static int raven_pcihost_init(SysBusDevice *dev) memory_region_init_io(&h->mmcfg, &PPC_PCIIO_ops, s, "pciio", 0x00400000); memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg); + memory_region_init_io(&s->intack, &PPC_intack_ops, s, "pci-intack", 1); + memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->intack); pci_create_simple(bus, 0, "raven"); return 0;